{"id":"https://openalex.org/W2886608444","doi":"https://doi.org/10.23919/mixdes.2018.8436623","title":"An Effect of Device Topology in VeSTIC Process on Logic Circuit Operation A Study Based on Ring Oscillator Operation Analysis","display_name":"An Effect of Device Topology in VeSTIC Process on Logic Circuit Operation A Study Based on Ring Oscillator Operation Analysis","publication_year":2018,"publication_date":"2018-06-01","ids":{"openalex":"https://openalex.org/W2886608444","doi":"https://doi.org/10.23919/mixdes.2018.8436623","mag":"2886608444"},"language":"en","primary_location":{"id":"doi:10.23919/mixdes.2018.8436623","is_oa":false,"landing_page_url":"https://doi.org/10.23919/mixdes.2018.8436623","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088307829","display_name":"Daniel Tomaszewski","orcid":"https://orcid.org/0000-0001-5158-2520"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Daniel Tomaszewski","raw_affiliation_strings":["Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland"],"affiliations":[{"raw_affiliation_string":"Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023874625","display_name":"K. Doma\u0144ski","orcid":"https://orcid.org/0000-0002-9741-0588"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Krzysztof Domanski","raw_affiliation_strings":["Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland"],"affiliations":[{"raw_affiliation_string":"Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056828147","display_name":"Grzegorz G\u0142uszko","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Grzegorz Gluszko","raw_affiliation_strings":["Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland"],"affiliations":[{"raw_affiliation_string":"Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069881770","display_name":"Andrzej Sierakowski","orcid":"https://orcid.org/0000-0002-1405-7839"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Andrzej Sierakowski","raw_affiliation_strings":["Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland"],"affiliations":[{"raw_affiliation_string":"Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084470814","display_name":"Dariusz Szmigiel","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Dariusz Szmigiel","raw_affiliation_strings":["Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland"],"affiliations":[{"raw_affiliation_string":"Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5088307829"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2575,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.56734833,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"51","last_page":"56"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.8692293763160706},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.6998034715652466},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.620182991027832},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5603377223014832},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.4974961578845978},{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.482496976852417},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.47747087478637695},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4472895860671997},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4414486587047577},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.414492130279541},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.41298648715019226},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.41030627489089966},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.38118335604667664},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.34459981322288513},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.19820129871368408}],"concepts":[{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.8692293763160706},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.6998034715652466},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.620182991027832},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5603377223014832},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.4974961578845978},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.482496976852417},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.47747087478637695},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4472895860671997},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4414486587047577},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.414492130279541},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.41298648715019226},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.41030627489089966},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.38118335604667664},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.34459981322288513},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.19820129871368408},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/mixdes.2018.8436623","is_oa":false,"landing_page_url":"https://doi.org/10.23919/mixdes.2018.8436623","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1595250909","https://openalex.org/W1597901969","https://openalex.org/W1616249851","https://openalex.org/W1722816743","https://openalex.org/W2026543046","https://openalex.org/W2112813001","https://openalex.org/W2161903232","https://openalex.org/W2290590898","https://openalex.org/W2470243148","https://openalex.org/W2565790730","https://openalex.org/W2735678755","https://openalex.org/W2744378522","https://openalex.org/W6635523124","https://openalex.org/W6637765068","https://openalex.org/W6676777394","https://openalex.org/W6683820115","https://openalex.org/W6696841707"],"related_works":["https://openalex.org/W2746929098","https://openalex.org/W2082591327","https://openalex.org/W4296473373","https://openalex.org/W1451738770","https://openalex.org/W2542280163","https://openalex.org/W2059422871","https://openalex.org/W1976440785","https://openalex.org/W2580743037","https://openalex.org/W3023368799","https://openalex.org/W2152533674"],"abstract_inverted_index":{"A":[0],"design":[1,59],"and":[2,72,101],"manufacturing":[3],"of":[4,9,32,44,80,96,116,126,130],"test":[5],"structures":[6],"for":[7,94,114],"characterization":[8,115],"logic":[10,24],"integrated":[11],"circuits":[12],"in":[13,18,66,120],"a":[14],"VeSTIC":[15,63,123],"process":[16,64,75],"developed":[17],"ITE,":[19],"have":[20,37,85,134],"been":[21,38,48,86,92,112,135],"described.":[22],"The":[23,40,108],"cell":[25],"static":[26],"characteristics":[27],"as":[28,30],"well":[29],"waveforms":[31],"the":[33,45,51,56,62,70,74,77,81,97,105,117,121,127,131],"53-stage":[34],"ring":[35,132],"oscillator":[36,133],"presented.":[39],"low":[41],"oscillation":[42],"frequency":[43],"circuit":[46,58,84,90],"has":[47,91,111],"attributed":[49],"to":[50],"parasitic":[52,78],"effects":[53],"induced":[54],"by":[55],"conservative":[57],"based":[60],"on":[61,69,73,104],"adopted":[65],"ITE.":[67],"Based":[68],"layout":[71],"specification,":[76],"elements":[79],"inverter":[82,98,119],"equivalent":[83,89],"extracted.":[87],"This":[88],"used":[93,113],"estimation":[95],"propagation":[99],"times":[100],"their":[102],"dependence":[103],"supply":[106],"bias.":[107],"same":[109],"approach":[110],"CMOS":[118],"ideal":[122],"process.":[124],"Frequencies":[125],"two":[128],"versions":[129],"calculated.":[136]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}