{"id":"https://openalex.org/W2744302273","doi":"https://doi.org/10.23919/mixdes.2017.8005194","title":"Designing HFPGA-based FSMs with counters","display_name":"Designing HFPGA-based FSMs with counters","publication_year":2017,"publication_date":"2017-06-01","ids":{"openalex":"https://openalex.org/W2744302273","doi":"https://doi.org/10.23919/mixdes.2017.8005194","mag":"2744302273"},"language":"en","primary_location":{"id":"doi:10.23919/mixdes.2017.8005194","is_oa":false,"landing_page_url":"https://doi.org/10.23919/mixdes.2017.8005194","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 MIXDES - 24th International Conference \"Mixed Design of Integrated Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114017949","display_name":"Alexander Barkalov","orcid":null},"institutions":[{"id":"https://openalex.org/I46305939","display_name":"University of Zielona G\u00f3ra","ror":"https://ror.org/04fzm7v55","country_code":"PL","type":"education","lineage":["https://openalex.org/I46305939"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Alexander Barkalov","raw_affiliation_strings":["Institute of Metrology, University of Zielona G\u00f3ra, Zielona G\u00f3ra, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Metrology, University of Zielona G\u00f3ra, Zielona G\u00f3ra, Poland","institution_ids":["https://openalex.org/I46305939"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079123162","display_name":"Larysa Titarenko","orcid":"https://orcid.org/0000-0001-9558-3322"},"institutions":[{"id":"https://openalex.org/I46305939","display_name":"University of Zielona G\u00f3ra","ror":"https://ror.org/04fzm7v55","country_code":"PL","type":"education","lineage":["https://openalex.org/I46305939"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Larysa Titarenko","raw_affiliation_strings":["Institute of Metrology, University of Zielona G\u00f3ra, Zielona G\u00f3ra, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Metrology, University of Zielona G\u00f3ra, Zielona G\u00f3ra, Poland","institution_ids":["https://openalex.org/I46305939"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029981129","display_name":"Jacek Bieganowski","orcid":"https://orcid.org/0000-0002-3566-6211"},"institutions":[{"id":"https://openalex.org/I46305939","display_name":"University of Zielona G\u00f3ra","ror":"https://ror.org/04fzm7v55","country_code":"PL","type":"education","lineage":["https://openalex.org/I46305939"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Jacek Bieganowski","raw_affiliation_strings":["Institute of Metrology, University of Zielona G\u00f3ra, Zielona G\u00f3ra, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Metrology, University of Zielona G\u00f3ra, Zielona G\u00f3ra, Poland","institution_ids":["https://openalex.org/I46305939"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I46305939"],"apc_list":null,"apc_paid":null,"fwci":0.2816,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.58495357,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"1702","issue":null,"first_page":"254","last_page":"257"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9908000230789185,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7396077513694763},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5739379525184631},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.544044017791748},{"id":"https://openalex.org/keywords/register","display_name":"Register (sociolinguistics)","score":0.528117299079895},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4877205789089203},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.4821281433105469},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4690228998661041},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.45909199118614197},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4557000398635864},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.41884639859199524},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.40103843808174133},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38049590587615967},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3215640187263489},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16640061140060425},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07736262679100037}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7396077513694763},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5739379525184631},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.544044017791748},{"id":"https://openalex.org/C2779235478","wikidata":"https://www.wikidata.org/wiki/Q286576","display_name":"Register (sociolinguistics)","level":2,"score":0.528117299079895},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4877205789089203},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.4821281433105469},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4690228998661041},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.45909199118614197},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4557000398635864},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.41884639859199524},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.40103843808174133},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38049590587615967},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3215640187263489},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16640061140060425},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07736262679100037},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/mixdes.2017.8005194","is_oa":false,"landing_page_url":"https://doi.org/10.23919/mixdes.2017.8005194","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 MIXDES - 24th International Conference \"Mixed Design of Integrated Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W251131796","https://openalex.org/W626514594","https://openalex.org/W1976773275","https://openalex.org/W2070477262","https://openalex.org/W2101276571","https://openalex.org/W2137038991","https://openalex.org/W2150864685","https://openalex.org/W2292811546","https://openalex.org/W2483541570","https://openalex.org/W4213095369","https://openalex.org/W4230904455","https://openalex.org/W4242021165","https://openalex.org/W6644394941","https://openalex.org/W6697211425"],"related_works":["https://openalex.org/W2535130387","https://openalex.org/W2205347728","https://openalex.org/W2188166871","https://openalex.org/W1531819087","https://openalex.org/W2045651232","https://openalex.org/W2017650358","https://openalex.org/W3013757523","https://openalex.org/W1966764473","https://openalex.org/W2059422871","https://openalex.org/W2013484291"],"abstract_inverted_index":{"A":[0],"method":[1,14],"is":[2,15,37],"proposed":[3,43],"for":[4],"hardware":[5],"reduction":[6],"of":[7,19,40,42],"HFPGA-based":[8],"Moore":[9],"FMS's":[10],"logic":[11],"circuit.":[12],"The":[13,25],"based":[16],"on":[17],"replacement":[18],"state":[20,23],"register":[21],"by":[22],"counter.":[24],"counter":[26],"can":[27],"be":[28],"increased":[29],"during":[30],"both":[31],"conditional":[32],"and":[33],"unconditional":[34],"transitions.":[35],"There":[36],"an":[38],"example":[39],"application":[41],"method.":[44]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}