{"id":"https://openalex.org/W2762572888","doi":"https://doi.org/10.23919/fpl.2017.8056819","title":"Find the real speed limit: FPGA CAD for chip-specific application delay measurement","display_name":"Find the real speed limit: FPGA CAD for chip-specific application delay measurement","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2762572888","doi":"https://doi.org/10.23919/fpl.2017.8056819","mag":"2762572888"},"language":"en","primary_location":{"id":"doi:10.23919/fpl.2017.8056819","is_oa":false,"landing_page_url":"https://doi.org/10.23919/fpl.2017.8056819","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100743340","display_name":"Ibrahim Ahmed","orcid":"https://orcid.org/0000-0003-2696-3086"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Ibrahim Ahmed","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103107245","display_name":"Shuze Zhao","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Shuze Zhao","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024463160","display_name":"Olivier Trescases","orcid":"https://orcid.org/0000-0002-7416-1320"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Olivier Trescases","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030184404","display_name":"Vaughn Betz","orcid":"https://orcid.org/0000-0003-0528-6493"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Vaughn Betz","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100743340"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.4506,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.62400286,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7709711790084839},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5733786821365356},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5717086791992188},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.5547206401824951},{"id":"https://openalex.org/keywords/measure","display_name":"Measure (data warehouse)","score":0.5381771922111511},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.4476121664047241},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4465470314025879},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.42836976051330566},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4130780100822449},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3580334186553955},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.31398171186447144},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.3014422059059143},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2454197108745575},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.14107149839401245},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10263219475746155},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.09181702136993408}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7709711790084839},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5733786821365356},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5717086791992188},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.5547206401824951},{"id":"https://openalex.org/C2780009758","wikidata":"https://www.wikidata.org/wiki/Q6804172","display_name":"Measure (data warehouse)","level":2,"score":0.5381771922111511},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.4476121664047241},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4465470314025879},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.42836976051330566},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4130780100822449},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3580334186553955},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.31398171186447144},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3014422059059143},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2454197108745575},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.14107149839401245},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10263219475746155},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.09181702136993408},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/fpl.2017.8056819","is_oa":false,"landing_page_url":"https://doi.org/10.23919/fpl.2017.8056819","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1967709031","https://openalex.org/W1991353737","https://openalex.org/W2005602803","https://openalex.org/W2006434824","https://openalex.org/W2022202043","https://openalex.org/W2045704975","https://openalex.org/W2096227207","https://openalex.org/W2098762322","https://openalex.org/W2102755988","https://openalex.org/W2106203961","https://openalex.org/W2120116751","https://openalex.org/W2129267471","https://openalex.org/W2136328167","https://openalex.org/W2141682861","https://openalex.org/W2150107614","https://openalex.org/W2150724867","https://openalex.org/W2154446814","https://openalex.org/W2170735577","https://openalex.org/W2525415380","https://openalex.org/W4254506919","https://openalex.org/W6675787411","https://openalex.org/W6679301951","https://openalex.org/W6680337182"],"related_works":["https://openalex.org/W4319430423","https://openalex.org/W4390224957","https://openalex.org/W4323831234","https://openalex.org/W2544043553","https://openalex.org/W4311839959","https://openalex.org/W2121309702","https://openalex.org/W1982685694","https://openalex.org/W49599899","https://openalex.org/W3217774925","https://openalex.org/W2040087757"],"abstract_inverted_index":{"Process":[0],"variation":[1],"is":[2,26],"increasing":[3],"with":[4,166],"each":[5,68],"successive":[6],"technology":[7],"node,":[8],"and":[9,49,129],"it":[10,138],"has":[11],"reached":[12],"the":[13,16,29,55,59,63,74,86,113,122,127,140,151,191],"point":[14],"where":[15],"worst-case":[17],"timing":[18],"modelling":[19],"employed":[20],"by":[21],"current":[22],"FPGA":[23,37],"CAD":[24,104],"tools":[25],"significantly":[27],"underutilizing":[28],"available":[30],"silicon.":[31],"Previous":[32],"studies":[33],"have":[34],"proposed":[35,56],"exploiting":[36],"reconfigurability":[38],"to":[39,61,111,134,181,195],"reduce":[40,190],"this":[41,94,98],"underutilization":[42],"using":[43],"techniques":[44],"such":[45,136],"as":[46],"late":[47],"binding":[48],"dynamic":[50],"voltage":[51],"scaling.":[52],"Most":[53],"of":[54,76,88,115,126,142,153,162,175,193],"solutions":[57],"require":[58],"ability":[60],"measure":[62,73,85,112],"target":[64],"application's":[65],"delay":[66,75,87,114,179],"on":[67,79,93,150],"configured":[69],"chip.":[70,96],"To":[71],"accurately":[72],"an":[77,144,177],"application":[78],"a":[80,102,148,160,182,199,206],"certain":[81],"chip,":[82],"we":[83,100,170,189],"must":[84],"its":[89],"speed":[90],"limiting":[91],"paths":[92,125,133],"specific":[95],"In":[97],"paper,":[99],"present":[101],"variation-aware":[103],"tool":[105,120],"that":[106,137,165],"automatically":[107],"generates":[108],"calibration":[109,155,168,187],"bitstreams":[110],"any":[116],"input":[117],"application.":[118],"Our":[119],"identifies":[121],"statistically":[123],"critical":[124],"circuit":[128],"optimally":[130],"selects":[131],"which":[132],"test":[135],"minimizes":[139],"chances":[141],"reporting":[143,176],"optimistic":[145,178],"delay,":[146],"under":[147],"constraint":[149],"number":[152],"allowed":[154],"bitstreams.":[156],"Experimental":[157],"results":[158],"across":[159],"suite":[161],"benchmarks":[163],"show":[164],"one":[167],"bitstream":[169],"achieve":[171],"16\u00d7":[172],"lower":[173,204],"probability":[174,192],"compared":[180],"greedy":[183,207],"approach.":[184,208],"With":[185],"three":[186],"bitstreams,":[188],"optimism":[194],"two":[196],"chips":[197],"in":[198],"million,":[200],"approximately":[201],"6,000":[202],"\u00d7":[203],"than":[205]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
