{"id":"https://openalex.org/W2762696783","doi":"https://doi.org/10.23919/fpl.2017.8056770","title":"PolyPC: Polymorphic parallel computing framework on embedded reconfigurable system","display_name":"PolyPC: Polymorphic parallel computing framework on embedded reconfigurable system","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2762696783","doi":"https://doi.org/10.23919/fpl.2017.8056770","mag":"2762696783"},"language":"en","primary_location":{"id":"doi:10.23919/fpl.2017.8056770","is_oa":false,"landing_page_url":"https://doi.org/10.23919/fpl.2017.8056770","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003927836","display_name":"Hongyuan Ding","orcid":null},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hongyuan Ding","raw_affiliation_strings":["Department of Computer Science and Computer Engineering, University of Arkansas, Fyetteville, Arkansas, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Computer Engineering, University of Arkansas, Fyetteville, Arkansas, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069173833","display_name":"Miaoqing Huang","orcid":"https://orcid.org/0000-0001-7376-3744"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Miaoqing Huang","raw_affiliation_strings":["Department of Computer Science and Computer Engineering, University of Arkansas, Fyetteville, Arkansas, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Computer Engineering, University of Arkansas, Fyetteville, Arkansas, USA","institution_ids":["https://openalex.org/I78715868"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5003927836"],"corresponding_institution_ids":["https://openalex.org/I78715868"],"apc_list":null,"apc_paid":null,"fwci":0.4506,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.62424098,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.9084126949310303},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8102719783782959},{"id":"https://openalex.org/keywords/microblaze","display_name":"MicroBlaze","score":0.8007763028144836},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6740347146987915},{"id":"https://openalex.org/keywords/executable","display_name":"Executable","score":0.6006125211715698},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5959110260009766},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.51661616563797},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5054137706756592},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4338666796684265},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.42738038301467896},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.275484561920166}],"concepts":[{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.9084126949310303},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8102719783782959},{"id":"https://openalex.org/C2777575374","wikidata":"https://www.wikidata.org/wiki/Q1644704","display_name":"MicroBlaze","level":3,"score":0.8007763028144836},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6740347146987915},{"id":"https://openalex.org/C160145156","wikidata":"https://www.wikidata.org/wiki/Q778586","display_name":"Executable","level":2,"score":0.6006125211715698},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5959110260009766},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.51661616563797},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5054137706756592},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4338666796684265},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.42738038301467896},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.275484561920166},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/fpl.2017.8056770","is_oa":false,"landing_page_url":"https://doi.org/10.23919/fpl.2017.8056770","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","score":0.4699999988079071,"display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1987163471","https://openalex.org/W2042431441","https://openalex.org/W2050732593","https://openalex.org/W2054951389","https://openalex.org/W2131355383","https://openalex.org/W2141597697","https://openalex.org/W2160126455","https://openalex.org/W2166029537","https://openalex.org/W2171429297","https://openalex.org/W2282596709","https://openalex.org/W2296385998"],"related_works":["https://openalex.org/W2376312311","https://openalex.org/W2354823813","https://openalex.org/W1612076744","https://openalex.org/W2152074211","https://openalex.org/W2126857316","https://openalex.org/W2129019972","https://openalex.org/W3164085601","https://openalex.org/W1522032972","https://openalex.org/W2139962137","https://openalex.org/W2113308450"],"abstract_inverted_index":{"With":[0],"the":[1,7,21,44,54,79,154],"help":[2],"of":[3,23,46,113,116,126,137],"parallelism":[4],"provided":[5],"by":[6,91],"fine-grained":[8],"architecture,":[9],"hardware":[10,34,75],"accelerators":[11],"on":[12,77],"Field":[13],"Programmable":[14],"Gate":[15],"Arrays":[16],"(FPGAs)":[17],"can":[18],"significantly":[19],"improve":[20,63],"performance":[22,67],"many":[24],"applications.":[25],"However,":[26],"designers":[27],"are":[28],"typically":[29],"required":[30],"to":[31,41,62,85,150],"have":[32],"excellent":[33],"programming":[35],"skills":[36],"and":[37,106,123],"unique":[38],"optimization":[39],"techniques":[40],"fully":[42],"explore":[43],"potential":[45],"FPGA":[47],"resources.":[48],"In":[49,140],"this":[50],"work,":[51],"we":[52],"propose":[53],"PolyPC":[55,70,80,98],"(Polymorphic":[56],"Parallel":[57],"Computing)":[58],"framework":[59,71,81,99],"that":[60],"aims":[61],"productivity":[64],"while":[65],"achieving":[66],"speedup.":[68],"The":[69,97,108],"implements":[72],"a":[73,111,119,129,144],"custom":[74],"platform":[76],"which":[78],"extends":[82],"vendor-provided":[83],"tools":[84],"convert":[86],"OpenCL-like":[87],"programs":[88],"into":[89],"executables":[90],"using":[92],"highlevel":[93],"synthesis":[94],"(HLS)":[95],"tools.":[96],"is":[100],"evaluated":[101],"regarding":[102],"performance,":[103],"area":[104,138],"efficiency,":[105],"multitasking.":[107],"results":[109],"show":[110],"maximum":[112],"66":[114],"folds":[115,125,136],"speedup":[117,127],"over":[118,128],"dual-core":[120],"ARM":[121],"processor,":[122,133],"1,043":[124],"high-performance":[130],"MicroBlaze":[131],"soft":[132],"with":[134,153],"125":[135],"efficiency.":[139],"addition,":[141],"it":[142],"delivers":[143],"significant":[145],"improvement":[146],"in":[147],"response":[148],"time":[149],"high-priority":[151],"PolyTasks":[152],"priority-aware":[155],"scheduling.":[156]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}