{"id":"https://openalex.org/W2763664021","doi":"https://doi.org/10.23919/fpl.2017.8056758","title":"A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis","display_name":"A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2763664021","doi":"https://doi.org/10.23919/fpl.2017.8056758","mag":"2763664021"},"language":"en","primary_location":{"id":"doi:10.23919/fpl.2017.8056758","is_oa":false,"landing_page_url":"https://doi.org/10.23919/fpl.2017.8056758","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://research-information.bris.ac.uk/files/150403630/Mohammad_Hosseinabady_A_Systematic_Approach_to_Design_and_Optimise_Streaming_Applications.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000075032","display_name":"Mohammad Hosseinabady","orcid":"https://orcid.org/0000-0003-3989-4999"},"institutions":[{"id":"https://openalex.org/I36234482","display_name":"University of Bristol","ror":"https://ror.org/0524sp257","country_code":"GB","type":"education","lineage":["https://openalex.org/I36234482"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Mohammad Hosseinabady","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Bristol, UK"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Bristol, UK","institution_ids":["https://openalex.org/I36234482"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005255540","display_name":"Jose Nunez\u2010Yanez","orcid":"https://orcid.org/0000-0002-5153-5481"},"institutions":[{"id":"https://openalex.org/I36234482","display_name":"University of Bristol","ror":"https://ror.org/0524sp257","country_code":"GB","type":"education","lineage":["https://openalex.org/I36234482"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Jose Luis Nunez-Yanez","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Bristol, UK"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Bristol, UK","institution_ids":["https://openalex.org/I36234482"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5000075032"],"corresponding_institution_ids":["https://openalex.org/I36234482"],"apc_list":null,"apc_paid":null,"fwci":0.4622,"has_fulltext":true,"cited_by_count":7,"citation_normalized_percentile":{"value":0.63337591,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8399081230163574},{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.7150230407714844},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6686497926712036},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6528675556182861},{"id":"https://openalex.org/keywords/loop-unrolling","display_name":"Loop unrolling","score":0.5744612216949463},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5494878888130188},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5020031929016113},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4860253930091858},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.47232383489608765},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.4569163918495178},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44388359785079956},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3822198212146759},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.281924307346344},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24309420585632324},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.12450924515724182},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10512727499008179},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09371837973594666}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8399081230163574},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.7150230407714844},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6686497926712036},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6528675556182861},{"id":"https://openalex.org/C76970557","wikidata":"https://www.wikidata.org/wiki/Q1869750","display_name":"Loop unrolling","level":3,"score":0.5744612216949463},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5494878888130188},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5020031929016113},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4860253930091858},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.47232383489608765},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4569163918495178},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44388359785079956},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3822198212146759},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.281924307346344},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24309420585632324},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12450924515724182},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10512727499008179},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09371837973594666},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.23919/fpl.2017.8056758","is_oa":false,"landing_page_url":"https://doi.org/10.23919/fpl.2017.8056758","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},{"id":"pmh:oai:research-information.bris.ac.uk:publications/0c140ff7-af6e-48fb-afd3-eb104e048b89","is_oa":true,"landing_page_url":"https://research-information.bris.ac.uk/en/publications/0c140ff7-af6e-48fb-afd3-eb104e048b89","pdf_url":"https://research-information.bris.ac.uk/files/150403630/Mohammad_Hosseinabady_A_Systematic_Approach_to_Design_and_Optimise_Streaming_Applications.pdf","source":{"id":"https://openalex.org/S4306400895","display_name":"Bristol Research (University of Bristol)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I36234482","host_organization_name":"University of Bristol","host_organization_lineage":["https://openalex.org/I36234482"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Hosseinabady, M & Nunez-Yanez, J L 2017, A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. in 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017., 8056758, Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.23919/FPL.2017.8056758","raw_type":"contributionToPeriodical"}],"best_oa_location":{"id":"pmh:oai:research-information.bris.ac.uk:publications/0c140ff7-af6e-48fb-afd3-eb104e048b89","is_oa":true,"landing_page_url":"https://research-information.bris.ac.uk/en/publications/0c140ff7-af6e-48fb-afd3-eb104e048b89","pdf_url":"https://research-information.bris.ac.uk/files/150403630/Mohammad_Hosseinabady_A_Systematic_Approach_to_Design_and_Optimise_Streaming_Applications.pdf","source":{"id":"https://openalex.org/S4306400895","display_name":"Bristol Research (University of Bristol)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I36234482","host_organization_name":"University of Bristol","host_organization_lineage":["https://openalex.org/I36234482"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Hosseinabady, M & Nunez-Yanez, J L 2017, A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. in 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017., 8056758, Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.23919/FPL.2017.8056758","raw_type":"contributionToPeriodical"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2657170112","display_name":null,"funder_award_id":"EP/L00321X/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G2722607983","display_name":null,"funder_award_id":"EP/N002539/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2763664021.pdf","grobid_xml":"https://content.openalex.org/works/W2763664021.grobid-xml"},"referenced_works_count":4,"referenced_works":["https://openalex.org/W1860183717","https://openalex.org/W2074785108","https://openalex.org/W2165973617","https://openalex.org/W2248652330"],"related_works":["https://openalex.org/W2921149022","https://openalex.org/W2461217932","https://openalex.org/W3206653210","https://openalex.org/W1044727952","https://openalex.org/W3003393365","https://openalex.org/W2156848920","https://openalex.org/W2267745769","https://openalex.org/W2398354748","https://openalex.org/W3088659733","https://openalex.org/W2794706380"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,11,31],"systematic":[4],"approach":[5],"to":[6,9,47,57,92,98,128],"help":[7],"designers":[8],"optimise":[10],"given":[12],"streaming":[13,32,101],"application":[14,33],"for":[15],"FPGAs":[16],"using":[17,107],"High-Level":[18],"Synthesis":[19],"(HLS).":[20],"The":[21,87,147],"proposed":[22,63],"technique":[23],"specifically":[24],"addresses":[25],"the":[26,37,44,49,53,62,68,76,99,108,119,139,145,151],"two":[27,65],"main":[28],"issues":[29],"in":[30,43,75,95],"that":[34],"are":[35,73,80,153],"determining":[36],"exact":[38],"amount":[39],"of":[40,132,138,150],"loop":[41,110],"unrolling":[42],"HLS":[45,120],"code":[46],"increase":[48],"throughput":[50,96],"and":[51,83,112],"finding":[52],"optimum":[54],"buffers'":[55],"size":[56],"prevent":[58],"deadlocks.":[59],"To":[60],"evaluate":[61],"techniques":[64],"applications":[66,79,125],"from":[67],"machine":[69],"learning":[70],"optimisation":[71],"area":[72],"studied":[74],"paper.":[77],"These":[78],"Hessian-vector":[81],"product":[82],"Conjugate":[84],"Gradient":[85],"(CG).":[86],"experimental":[88],"results":[89],"show":[90,126],"up":[91,127],"38\u00d7":[93],"speed-up":[94],"compared":[97],"original":[100],"implementations":[102],"provided":[103,117],"by":[104,118],"knowledgeable":[105],"engineers":[106],"dataflow,":[109],"pipelining":[111],"FIFO":[113],"channel":[114],"related":[115],"pragmas":[116],"tool.":[121],"In":[122],"addition,":[123],"these":[124],"2.98":[129],"GB/sec":[130],"usage":[131],"memory":[133,141],"bandwidth":[134,142],"which":[135],"is":[136],"93.1%":[137],"total":[140],"available":[143,154],"on":[144],"system.":[146],"source":[148],"codes":[149],"designs":[152],"at":[155],"https://github.com/Hosseinabady/csdfg-hls.":[156]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-03-16T09:10:04.655348","created_date":"2025-10-10T00:00:00"}
