{"id":"https://openalex.org/W7163555731","doi":"https://doi.org/10.23919/date69613.2026.11539602","title":"Late Breaking Results: Efficient Formal Verification of Highly Optimized MAC Units","display_name":"Late Breaking Results: Efficient Formal Verification of Highly Optimized MAC Units","publication_year":2026,"publication_date":"2026-04-20","ids":{"openalex":"https://openalex.org/W7163555731","doi":"https://doi.org/10.23919/date69613.2026.11539602"},"language":null,"primary_location":{"id":"doi:10.23919/date69613.2026.11539602","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date69613.2026.11539602","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 Design, Automation & Test in Europe Conference (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054997895","display_name":"Jan Kleinekath\u00f6fer","orcid":"https://orcid.org/0000-0001-6357-0914"},"institutions":[{"id":"https://openalex.org/I180437899","display_name":"University of Bremen","ror":"https://ror.org/04ers2y35","country_code":"DE","type":"education","lineage":["https://openalex.org/I180437899"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jan Kleinekath\u00f6fer","raw_affiliation_strings":["University of Bremen,Institute of Computer Science,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Bremen,Institute of Computer Science,Germany","institution_ids":["https://openalex.org/I180437899"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060500371","display_name":"Lennart Weingarten","orcid":"https://orcid.org/0009-0005-6316-9780"},"institutions":[{"id":"https://openalex.org/I180437899","display_name":"University of Bremen","ror":"https://ror.org/04ers2y35","country_code":"DE","type":"education","lineage":["https://openalex.org/I180437899"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Lennart Weingarten","raw_affiliation_strings":["University of Bremen,Institute of Computer Science,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Bremen,Institute of Computer Science,Germany","institution_ids":["https://openalex.org/I180437899"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5137825263","display_name":"Kamalika Datta","orcid":null},"institutions":[{"id":"https://openalex.org/I33256026","display_name":"German Research Centre for Artificial Intelligence","ror":"https://ror.org/01ayc5b57","country_code":"DE","type":"funder","lineage":["https://openalex.org/I33256026"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Kamalika Datta","raw_affiliation_strings":["German Research Centre for Artificial Intelligence (DFKI),Bremen,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"German Research Centre for Artificial Intelligence (DFKI),Bremen,Germany","institution_ids":["https://openalex.org/I33256026"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071742136","display_name":"Rolf Drechsler","orcid":"https://orcid.org/0000-0002-9872-1740"},"institutions":[{"id":"https://openalex.org/I33256026","display_name":"German Research Centre for Artificial Intelligence","ror":"https://ror.org/01ayc5b57","country_code":"DE","type":"funder","lineage":["https://openalex.org/I33256026"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rolf Drechsler","raw_affiliation_strings":["German Research Centre for Artificial Intelligence (DFKI),Bremen,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"German Research Centre for Artificial Intelligence (DFKI),Bremen,Germany","institution_ids":["https://openalex.org/I33256026"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.9173046,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.3303000032901764,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.3303000032901764,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.12120000272989273,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.07400000095367432,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.47510001063346863},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.38089999556541443},{"id":"https://openalex.org/keywords/software-verification","display_name":"Software verification","score":0.28679999709129333},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.2736999988555908},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.27309998869895935},{"id":"https://openalex.org/keywords/formal-specification","display_name":"Formal specification","score":0.26899999380111694}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6585999727249146},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.47510001063346863},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.38089999556541443},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29739999771118164},{"id":"https://openalex.org/C33054407","wikidata":"https://www.wikidata.org/wiki/Q6504747","display_name":"Software verification","level":5,"score":0.28679999709129333},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2849999964237213},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2761000096797943},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.2736999988555908},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.27309998869895935},{"id":"https://openalex.org/C116253237","wikidata":"https://www.wikidata.org/wiki/Q1437424","display_name":"Formal specification","level":2,"score":0.26899999380111694},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.25679999589920044},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.2565999925136566},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2547000050544739}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date69613.2026.11539602","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date69613.2026.11539602","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 Design, Automation & Test in Europe Conference (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1604160780","https://openalex.org/W2768948804","https://openalex.org/W2798446820","https://openalex.org/W2916007847","https://openalex.org/W3036041789","https://openalex.org/W3165204519","https://openalex.org/W4401568143","https://openalex.org/W4410582686","https://openalex.org/W4414433374"],"related_works":[],"abstract_inverted_index":{"The":[0,18],"demand":[1],"for":[2,56],"compute-intensive":[3],"applications":[4],"such":[5],"as":[6],"AI/ML":[7],"has":[8],"led":[9],"to":[10,37,43],"the":[11,38,45,71,76],"development":[12],"of":[13,79],"processors":[14],"with":[15],"complex":[16],"functionalities.":[17],"Multiply":[19],"Accumulate":[20],"(MAC)":[21],"unit":[22],"is":[23,33],"a":[24,62,88],"vital":[25],"component":[26],"in":[27,84],"these":[28],"processors,":[29],"but":[30],"its":[31],"verification":[32,60],"very":[34],"challenging":[35],"due":[36],"highly":[39],"optimized":[40,57],"designs":[41],"used":[42],"implement":[44],"MAC":[46,58,86],"operation.":[47],"In":[48],"this":[49],"paper,":[50],"we":[51,74],"show":[52],"some":[53],"interesting":[54],"results":[55],"design":[59],"using":[61,92],"formal":[63],"proof":[64,95],"engine,":[65],"Symbolic":[66],"Computer":[67],"Algebra":[68],"(SCA).":[69],"For":[70],"first":[72],"time,":[73],"exploit":[75],"combined":[77],"benefit":[78],"phase":[80],"and":[81],"dynamic":[82],"ordering":[83],"verifying":[85],"circuits,":[87],"capability":[89],"not":[90],"possible":[91],"state-of-the-art":[93],"SCA":[94],"engines.":[96]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2026-06-05T00:00:00"}