{"id":"https://openalex.org/W7163530627","doi":"https://doi.org/10.23919/date69613.2026.11539284","title":"RouterAcc: FPGA Acceleration for VLSI Detailed Router via Hierarchical Storage Mapping","display_name":"RouterAcc: FPGA Acceleration for VLSI Detailed Router via Hierarchical Storage Mapping","publication_year":2026,"publication_date":"2026-04-20","ids":{"openalex":"https://openalex.org/W7163530627","doi":"https://doi.org/10.23919/date69613.2026.11539284"},"language":null,"primary_location":{"id":"doi:10.23919/date69613.2026.11539284","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date69613.2026.11539284","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 Design, Automation & Test in Europe Conference (DATE)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5137909505","display_name":"Ruiyuan Guo","orcid":null},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ruiyuan Guo","raw_affiliation_strings":["Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China","institution_ids":["https://openalex.org/I4210132426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043615810","display_name":"Zexu Zhang","orcid":"https://orcid.org/0009-0003-0931-2414"},"institutions":[{"id":"https://openalex.org/I80947539","display_name":"Fuzhou University","ror":"https://ror.org/011xvna82","country_code":"CN","type":"education","lineage":["https://openalex.org/I80947539"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zexu Zhang","raw_affiliation_strings":["Fuzhou University,College of Computer and Big Data,Fuzhou,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fuzhou University,College of Computer and Big Data,Fuzhou,China","institution_ids":["https://openalex.org/I80947539"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5137809705","display_name":"Chang Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chang Liu","raw_affiliation_strings":["Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China","institution_ids":["https://openalex.org/I4210132426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5137910185","display_name":"Da Tang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Da Tang","raw_affiliation_strings":["Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China","institution_ids":["https://openalex.org/I4210132426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003842661","display_name":"Weiqi Shen","orcid":"https://orcid.org/0000-0001-6203-0182"},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weiqi Shen","raw_affiliation_strings":["Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China","institution_ids":["https://openalex.org/I4210132426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047412399","display_name":"Haodong Lu","orcid":"https://orcid.org/0000-0002-8628-2664"},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Haodong Lu","raw_affiliation_strings":["Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China","institution_ids":["https://openalex.org/I4210132426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101183675","display_name":"Xiqiong Bai","orcid":null},"institutions":[{"id":"https://openalex.org/I41198531","display_name":"Nanjing University of Posts and Telecommunications","ror":"https://ror.org/043bpky34","country_code":"CN","type":"education","lineage":["https://openalex.org/I41198531"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiqiong Bai","raw_affiliation_strings":["Nanjing University of Posts and Telecommunications,School of Integrated Circuit Science and Engineering,Nanjing,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nanjing University of Posts and Telecommunications,School of Integrated Circuit Science and Engineering,Nanjing,China","institution_ids":["https://openalex.org/I41198531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5137831922","display_name":"Kun Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kun Wang","raw_affiliation_strings":["Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China","institution_ids":["https://openalex.org/I4210132426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5137824638","display_name":"Jianli Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianli Chen","raw_affiliation_strings":["Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China","institution_ids":["https://openalex.org/I4210132426"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103746088","display_name":"Jie Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Yu","raw_affiliation_strings":["Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab of Integrated Chips & Systems, and School of Microelectronics,China","institution_ids":["https://openalex.org/I4210132426"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.41130000352859497,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.41130000352859497,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.22759999334812164,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.18930000066757202,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.597599983215332},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5932000279426575},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.5101000070571899},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.42739999294281006},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.27399998903274536},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.26260000467300415}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6340000033378601},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.597599983215332},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5932000279426575},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.5101000070571899},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.42739999294281006},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42160001397132874},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3635999858379364},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.29249998927116394},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.27399998903274536},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.26260000467300415},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.2572999894618988},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.25290000438690186},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25279998779296875},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.25110000371932983}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date69613.2026.11539284","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date69613.2026.11539284","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 Design, Automation & Test in Europe Conference (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7107006907463074,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1985622999","https://openalex.org/W2022844803","https://openalex.org/W2029130826","https://openalex.org/W2793662773","https://openalex.org/W2966209785","https://openalex.org/W2997936488","https://openalex.org/W2997948262","https://openalex.org/W2998517322","https://openalex.org/W3036410182","https://openalex.org/W3078187042","https://openalex.org/W3092390201","https://openalex.org/W3092633010","https://openalex.org/W3160984420","https://openalex.org/W4206621496","https://openalex.org/W4212975207","https://openalex.org/W4285232152"],"related_works":[],"abstract_inverted_index":{"Detailed":[0],"routing":[1,155],"constitutes":[2],"a":[3,74,84,90,105,115],"critical":[4],"phase":[5],"in":[6,24],"the":[7,17,25,126,167],"very":[8],"large-scale":[9],"integration":[10],"(VLSI)":[11],"physical":[12],"design,":[13],"widely":[14],"regarded":[15],"as":[16,164,166],"most":[18],"time-consuming":[19],"and":[20,34,47,73,89,98,114,160],"computationally":[21],"intensive":[22],"step":[23],"back-end":[26],"design":[27],"process.":[28],"Due":[29],"to":[30,78,94,119,158],"its":[31],"iterative":[32],"nature":[33],"strong":[35],"data":[36,100,116],"dependencies,":[37],"conventional":[38],"parallel":[39],"acceleration":[40,60],"techniques":[41],"often":[42],"suffer":[43],"from":[44],"limited":[45],"scalability":[46],"effectiveness.":[48],"To":[49],"address":[50],"these":[51],"challenges,":[52],"we":[53,82],"propose":[54],"RouterAcc,":[55],"an":[56,69],"FPGA-based":[57,170],"software\u2013hardware":[58],"co-design":[59],"framework":[61],"tailored":[62],"for":[63],"VLSI":[64],"detailed":[65],"routing.":[66],"RouterAcc":[67,103,131,148],"incorporates":[68],"access":[70],"analysis":[71],"mechanism":[72],"termination":[75],"condition":[76],"strategy":[77,118],"accelerate":[79],"convergence.":[80],"Furthermore,":[81],"employ":[83],"hierarchical":[85,106],"storage":[86],"mapping":[87],"scheme":[88],"flexible":[91],"dimension-partitioning":[92],"architecture":[93],"alleviate":[95],"memory":[96],"bottlenecks":[97],"enhance":[99],"locality.":[101],"Additionally,":[102],"leverages":[104],"comparison":[107],"pipeline":[108],"with":[109,139],"fully":[110],"parallelized":[111],"computing":[112],"units":[113],"preprocessing":[117],"maximize":[120],"computational":[121],"efficiency.":[122],"Experimental":[123],"results":[124],"on":[125],"ISPD\u201918":[127],"benchmarks":[128],"demonstrate":[129],"that":[130],"achieves":[132],"consistent":[133],"speedups":[134,150],"of":[135,151],"2.1\u00d7\u20132.3\u00d7":[136],"over":[137],"TritonRoute":[138,159],"less":[140],"than":[141],"1%":[142],"quality":[143,156],"degradation.":[144],"With":[145],"further":[146],"co-optimization,":[147],"attains":[149],"2.7\u00d7\u201311.8\u00d7":[152],"while":[153],"maintaining":[154],"comparable":[157],"surpassing":[161],"Dr.CU":[162],"2.0":[163],"well":[165],"state-of-the-art":[168],"(SOTA)":[169],"approaches.":[171]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2026-06-05T00:00:00"}