{"id":"https://openalex.org/W4410582432","doi":"https://doi.org/10.23919/date64628.2025.10993276","title":"Multiscale Feature Attention and Transformer Based Congestion Prediction for Routability-Driven FPGA Macro Placement","display_name":"Multiscale Feature Attention and Transformer Based Congestion Prediction for Routability-Driven FPGA Macro Placement","publication_year":2025,"publication_date":"2025-03-31","ids":{"openalex":"https://openalex.org/W4410582432","doi":"https://doi.org/10.23919/date64628.2025.10993276"},"language":"en","primary_location":{"id":"doi:10.23919/date64628.2025.10993276","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date64628.2025.10993276","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Design, Automation & Test in Europe Conference (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050333667","display_name":"Hao Gu","orcid":"https://orcid.org/0000-0002-3110-2531"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Hao Gu","raw_affiliation_strings":["Southeast University,Dept. of National ASIC System Center,Nanjing,China"],"affiliations":[{"raw_affiliation_string":"Southeast University,Dept. of National ASIC System Center,Nanjing,China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071328619","display_name":"Xinglin Zheng","orcid":"https://orcid.org/0009-0008-4182-4328"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xinglin Zheng","raw_affiliation_strings":["Southeast University,Dept. of National ASIC System Center,Nanjing,China"],"affiliations":[{"raw_affiliation_string":"Southeast University,Dept. of National ASIC System Center,Nanjing,China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072895561","display_name":"Youwen Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Youwen Wang","raw_affiliation_strings":["Southeast University,Dept. of National ASIC System Center,Nanjing,China"],"affiliations":[{"raw_affiliation_string":"Southeast University,Dept. of National ASIC System Center,Nanjing,China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081768224","display_name":"Keyu Peng","orcid":"https://orcid.org/0009-0004-2438-726X"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Keyu Peng","raw_affiliation_strings":["Southeast University,Dept. of National ASIC System Center,Nanjing,China"],"affiliations":[{"raw_affiliation_string":"Southeast University,Dept. of National ASIC System Center,Nanjing,China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065790763","display_name":"Ziran Zhu","orcid":"https://orcid.org/0000-0002-9475-6364"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ziran Zhu","raw_affiliation_strings":["Southeast University,Dept. of National ASIC System Center,Nanjing,China"],"affiliations":[{"raw_affiliation_string":"Southeast University,Dept. of National ASIC System Center,Nanjing,China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030384645","display_name":"Jun Yang","orcid":"https://orcid.org/0000-0002-8379-0321"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Yang","raw_affiliation_strings":["Southeast University,Dept. of National ASIC System Center,Nanjing,China"],"affiliations":[{"raw_affiliation_string":"Southeast University,Dept. of National ASIC System Center,Nanjing,China","institution_ids":["https://openalex.org/I76569877"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5050333667"],"corresponding_institution_ids":["https://openalex.org/I76569877"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1184739,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7724709510803223},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.7121363878250122},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6993606686592102},{"id":"https://openalex.org/keywords/transformer","display_name":"Transformer","score":0.5514307618141174},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5052545666694641},{"id":"https://openalex.org/keywords/feature","display_name":"Feature (linguistics)","score":0.4783701002597809},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3831755220890045},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.3517456650733948},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18977904319763184},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.18405520915985107},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.104056715965271}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7724709510803223},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.7121363878250122},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6993606686592102},{"id":"https://openalex.org/C66322947","wikidata":"https://www.wikidata.org/wiki/Q11658","display_name":"Transformer","level":3,"score":0.5514307618141174},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5052545666694641},{"id":"https://openalex.org/C2776401178","wikidata":"https://www.wikidata.org/wiki/Q12050496","display_name":"Feature (linguistics)","level":2,"score":0.4783701002597809},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3831755220890045},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3517456650733948},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18977904319763184},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.18405520915985107},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.104056715965271},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date64628.2025.10993276","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date64628.2025.10993276","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Design, Automation & Test in Europe Conference (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G4105230798","display_name":null,"funder_award_id":"92373207,62104037","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G5073227778","display_name":null,"funder_award_id":"2242024RCB0052","funder_id":"https://openalex.org/F4320324856","funder_display_name":"Southeast University"},{"id":"https://openalex.org/G5200715922","display_name":null,"funder_award_id":"2022YFB4400500","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320324856","display_name":"Southeast University","ror":"https://ror.org/04ct4d772"},{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1901129140","https://openalex.org/W2031974129","https://openalex.org/W2194775991","https://openalex.org/W2899885603","https://openalex.org/W2955058313","https://openalex.org/W3041521987","https://openalex.org/W3125127664","https://openalex.org/W3140720939","https://openalex.org/W4212918377","https://openalex.org/W4226039771","https://openalex.org/W4388079952","https://openalex.org/W4401414256","https://openalex.org/W6846588798","https://openalex.org/W6858427843"],"related_works":["https://openalex.org/W2030816003","https://openalex.org/W4239992647","https://openalex.org/W2150013480","https://openalex.org/W1554458299","https://openalex.org/W81423522","https://openalex.org/W1509860481","https://openalex.org/W2488264085","https://openalex.org/W2076325756","https://openalex.org/W4386206750","https://openalex.org/W4238700786"],"abstract_inverted_index":{"As":[0],"routability":[1,43,227],"has":[2],"emerged":[3],"as":[4,51],"a":[5,37,61,105],"critical":[6,38],"task":[7],"in":[8],"modern":[9],"field-programmable":[10],"gate":[11],"array":[12],"(FPGA)":[13],"physical":[14],"design,":[15],"it":[16],"is":[17,36,94,109],"desirable":[18],"to":[19,72,97,123,149,170,188],"develop":[20],"an":[21],"effective":[22,84],"congestion":[23,34,69,156,182,217],"prediction":[24,70,218],"model":[25,53,71,144,214,222],"during":[26],"the":[27,32,42,52,113,125,178,186,194,202,225,231,237],"placement":[28,74,207],"stage.":[29],"Given":[30],"that":[31,49,111,163,212],"interconnection":[33],"level":[35,50,157],"metric":[39],"for":[40,83],"measuring":[41],"of":[44,127],"FPGA":[45,85,205],"placement,":[46],"we":[47,59],"utilize":[48],"training":[54],"label.":[55],"In":[56],"this":[57],"paper,":[58],"propose":[60],"multiscale":[62,99,129],"feature":[63],"attention":[64,115,166],"(MFA)":[65],"and":[66,76,120,135,152,184,198,228],"transformer":[67,161],"based":[68,240],"extract":[73,98,171],"features":[75,100,151],"strengthen":[77],"their":[78],"association":[79],"with":[80],"congested":[81,197],"areas":[82],"macro":[86,206,238],"placement.":[87,103],"A":[88],"convolutional":[89],"neural":[90],"network":[91],"(CNN)":[92],"component":[93],"first":[95],"designed":[96],"from":[101,201],"grid-based":[102],"Then,":[104],"well-designed":[106],"MFA":[107,133],"block":[108],"proposed":[110],"utilizes":[112],"dual":[114],"mechanism":[116],"on":[117,193,241],"both":[118],"spatial":[119],"channel":[121],"dimensions":[122],"enhance":[124,185],"representation":[126],"each":[128,139],"feature.":[130],"By":[131],"incorporating":[132],"blocks":[134],"CNN's":[136],"output":[137],"at":[138],"skip":[140],"connection":[141],"layer,":[142],"our":[143,213,221],"substantially":[145],"enhances":[146],"its":[147],"capability":[148],"learn":[150],"recover":[153],"more":[154],"precise":[155],"maps.":[158],"Furthermore,":[159,220],"multiple":[160],"layers":[162],"employ":[164],"dynamic":[165],"mechanisms":[167],"are":[168],"utilized":[169],"global":[172],"information,":[173],"which":[174],"can":[175,223],"significantly":[176],"improve":[177],"difference":[179],"between":[180],"various":[181],"levels":[183],"ability":[187],"identify":[189],"these":[190],"levels.":[191],"Based":[192],"ten":[195],"most":[196],"challenging":[199],"benchmarks":[200],"MLCAD":[203],"2023":[204],"contest,":[208],"experimental":[209],"results":[210],"show":[211],"outperforms":[215],"existing":[216],"models.":[219],"achieve":[224],"best":[226],"score":[229],"among":[230],"contest":[232],"winners":[233],"when":[234],"integrated":[235],"into":[236],"placer":[239],"DREAMPlaceFPGA.":[242]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}