{"id":"https://openalex.org/W4410582853","doi":"https://doi.org/10.23919/date64628.2025.10993219","title":"ASHES 1.5: Analog Computing Synthesis for FPAAs and ASICs","display_name":"ASHES 1.5: Analog Computing Synthesis for FPAAs and ASICs","publication_year":2025,"publication_date":"2025-03-31","ids":{"openalex":"https://openalex.org/W4410582853","doi":"https://doi.org/10.23919/date64628.2025.10993219"},"language":"en","primary_location":{"id":"doi:10.23919/date64628.2025.10993219","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date64628.2025.10993219","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Design, Automation &amp;amp; Test in Europe Conference (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5093834563","display_name":"Afolabi Ige","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Afolabi Ige","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology,Atlanta,GA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology,Atlanta,GA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073433071","display_name":"Jennifer Hasler","orcid":"https://orcid.org/0000-0002-6866-3156"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jennifer Hasler","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology,Atlanta,GA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology,Atlanta,GA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5093834563"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":7.3583,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.96674197,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9082000255584717,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9082000255584717,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6090183258056641},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5651738047599792},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.363365113735199},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.293046772480011}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6090183258056641},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5651738047599792},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.363365113735199},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.293046772480011}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date64628.2025.10993219","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date64628.2025.10993219","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Design, Automation &amp;amp; Test in Europe Conference (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W2007456112","https://openalex.org/W2043684831","https://openalex.org/W2124339910","https://openalex.org/W2124704320","https://openalex.org/W2138383740","https://openalex.org/W2253818459","https://openalex.org/W2343850787","https://openalex.org/W2757408529","https://openalex.org/W2767787194","https://openalex.org/W2903126441","https://openalex.org/W3084745515","https://openalex.org/W3108107800","https://openalex.org/W3114230949","https://openalex.org/W3139118283","https://openalex.org/W4379115958","https://openalex.org/W4384947595","https://openalex.org/W4390874830","https://openalex.org/W4391410259","https://openalex.org/W4391696986","https://openalex.org/W4401691577","https://openalex.org/W4403060182","https://openalex.org/W4404316942"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2165367082","https://openalex.org/W1972641423","https://openalex.org/W611446063","https://openalex.org/W2390279801","https://openalex.org/W4391913857","https://openalex.org/W2358668433","https://openalex.org/W4396701345"],"abstract_inverted_index":{"Synthesis":[0],"tools":[1,59,61],"can":[2,86,115],"unlock":[3],"the":[4],"potential":[5],"of":[6,63,92],"analog":[7,35,77,123],"architectures":[8],"to":[9],"achieve":[10],"real-time":[11],"computation,":[12],"signal":[13],"processing,":[14],"inference":[15],"and":[16,31,36,42,101,124],"learning":[17],"for":[18,40],"low":[19],"<tex":[20],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[21],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$S$</tex>WaP":[22],"systems":[23],"in":[24],"commercial":[25],"timescales.":[26],"We":[27],"present":[28],"a":[29,90],"methodology":[30],"results":[32],"towards":[33,127],"system":[34],"mixed-signal":[37,79,125],"synthesis":[38,69],"both":[39],"FPAAs":[41],"Custom":[43],"Analog":[44,55],"IC":[45,68],"design.":[46],"Building":[47],"on":[48,51,76],"previously":[49],"efforts":[50],"large-scale":[52],"Field":[53],"Programmable":[54],"Arrays":[56],"(FPAA)":[57],"targeting":[58],"enables":[60],"capable":[62],"synthesizing":[64],"new":[65],"ICs.":[66],"The":[67,104],"is":[70,107],"built":[71],"upon":[72],"our":[73],"recent":[74],"work":[75],"&":[78],"programmable":[80],"CMOS":[81,93],"standard":[82],"cell":[83],"library":[84],"that":[85,114],"be":[87,116],"used":[88],"across":[89],"range":[91],"process":[94],"nodes":[95],"(e.g.":[96],"180nm,":[97],"130nm,":[98],"65nm,":[99],"28nm,":[100],"16nm":[102],"CMOS).":[103],"entire":[105],"tool-flow":[106],"being":[108],"developed":[109],"as":[110],"an":[111],"open-source":[112],"tool":[113],"widely":[117],"available.":[118],"These":[119],"approaches":[120],"enable":[121],"moving":[122],"design":[126],"structured":[128],"Design":[129],"Space":[130],"Exploration":[131],"(DSE).":[132]},"counts_by_year":[{"year":2025,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
