{"id":"https://openalex.org/W4410584198","doi":"https://doi.org/10.23919/date64628.2025.10993030","title":"Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables","display_name":"Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables","publication_year":2025,"publication_date":"2025-03-31","ids":{"openalex":"https://openalex.org/W4410584198","doi":"https://doi.org/10.23919/date64628.2025.10993030"},"language":"en","primary_location":{"id":"doi:10.23919/date64628.2025.10993030","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date64628.2025.10993030","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Design, Automation & Test in Europe Conference (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Subhadip Ghosh","orcid":null},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Subhadip Ghosh","raw_affiliation_strings":["University of Minnesota,Department of Electrical and Computer Engineering,Minneapolis,MN,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota,Department of Electrical and Computer Engineering,Minneapolis,MN,USA","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5116187640","display_name":"Endalk Y. Gebru","orcid":null},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Endalk Y. Gebru","raw_affiliation_strings":["University of Minnesota,Department of Electrical and Computer Engineering,Minneapolis,MN,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota,Department of Electrical and Computer Engineering,Minneapolis,MN,USA","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110899319","display_name":"Chandramouli Kashyap","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chandramouli V. Kashyap","raw_affiliation_strings":["Cadence Design Systems,Portland,OR,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems,Portland,OR,USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059037025","display_name":"Ramesh Harjani","orcid":"https://orcid.org/0000-0001-7691-566X"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ramesh Harjani","raw_affiliation_strings":["University of Minnesota,Department of Electrical and Computer Engineering,Minneapolis,MN,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota,Department of Electrical and Computer Engineering,Minneapolis,MN,USA","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068714995","display_name":"Sachin S. Sapatnekar","orcid":"https://orcid.org/0000-0002-5353-2364"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sachin S. Sapatnekar","raw_affiliation_strings":["University of Minnesota,Department of Electrical and Computer Engineering,Minneapolis,MN,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota,Department of Electrical and Computer Engineering,Minneapolis,MN,USA","institution_ids":["https://openalex.org/I130238516"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":6.9512,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.96664972,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9811000227928162,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9811000227928162,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9688000082969666,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9628000259399414,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7257647514343262},{"id":"https://openalex.org/keywords/transformer","display_name":"Transformer","score":0.6065758466720581},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5940783023834229},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.5614644289016724},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4898318946361542},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44532105326652527},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3601149320602417},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.23847469687461853},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15185651183128357}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7257647514343262},{"id":"https://openalex.org/C66322947","wikidata":"https://www.wikidata.org/wiki/Q11658","display_name":"Transformer","level":3,"score":0.6065758466720581},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5940783023834229},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.5614644289016724},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4898318946361542},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44532105326652527},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3601149320602417},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.23847469687461853},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15185651183128357},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date64628.2025.10993030","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date64628.2025.10993030","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Design, Automation & Test in Europe Conference (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8600000143051147,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1812927916","https://openalex.org/W1964239621","https://openalex.org/W1999357165","https://openalex.org/W2010307518","https://openalex.org/W2065183815","https://openalex.org/W2096249093","https://openalex.org/W2106476087","https://openalex.org/W2163565880","https://openalex.org/W2167034725","https://openalex.org/W2167493278","https://openalex.org/W2758603753","https://openalex.org/W2769791151","https://openalex.org/W2791591274","https://openalex.org/W2962784628","https://openalex.org/W3036532492","https://openalex.org/W3092618035","https://openalex.org/W3111226333","https://openalex.org/W3203408580","https://openalex.org/W3204161648","https://openalex.org/W4385245566","https://openalex.org/W4386764902"],"related_works":["https://openalex.org/W2375311683","https://openalex.org/W2366062860","https://openalex.org/W2373777250","https://openalex.org/W2353956655","https://openalex.org/W2020653254","https://openalex.org/W2010454064","https://openalex.org/W2352072014","https://openalex.org/W217279133","https://openalex.org/W2393487946","https://openalex.org/W2373310108"],"abstract_inverted_index":{"Device":[0],"sizing":[1,19,174],"is":[2,52,83,164],"crucial":[3],"for":[4,142,188],"meeting":[5,181],"performance":[6,77],"specifications":[7,43,182],"in":[8,90,132,180],"operational":[9],"transconductance":[10],"amplifiers":[11],"(OTAs),":[12],"and":[13,41,135,172,190],"this":[14],"work":[15],"proposes":[16],"an":[17,38],"automated":[18],"framework":[20,128],"based":[21],"on":[22,65,166],"a":[23,66,105,167],"transformer":[24,64,81],"model.":[25],"The":[26,94,162],"approach":[27,51,109],"first":[28],"leverages":[29],"the":[30,55,60,63,79,91,112,126,140,147,158,173],"driving-point":[31],"signal":[32],"flow":[33],"graph":[34],"(DP-SFG)":[35],"to":[36,54,58,85,101,120,157],"map":[37],"OTA":[39,70],"circuit":[40],"its":[42],"into":[44],"transformer-friendly":[45],"sequential":[46,56],"data.":[47],"A":[48],"specialized":[49],"tokenization":[50],"applied":[53],"data":[57],"expedite":[59],"training":[61,160],"of":[62,69,169],"diverse":[67],"range":[68],"topologies,":[71],"under":[72],"multiple":[73],"specifications.":[74],"Under":[75],"specific":[76],"constraints,":[78],"trained":[80],"model":[82],"used":[84],"accurately":[86],"predict":[87],"DP-SFG":[88,96],"parameters":[89,97],"inference":[92],"phase.":[93,161],"predicted":[95],"are":[98,155],"then":[99],"translated":[100],"transistor":[102],"sizes":[103],"using":[104],"precomputed":[106],"look-up":[107],"table-based":[108],"inspired":[110],"by":[111,138],"9m":[113],"/":[114],"I":[115],"d":[116],"methodology.":[117],"In":[118],"contrast":[119],"previous":[121],"conventional":[122],"or":[123],"machine-learning-based":[124],"methods,":[125],"proposed":[127],"achieves":[129],"significant":[130],"improvements":[131],"both":[133],"speed":[134],"computational":[136],"efficiency":[137],"reducing":[139],"need":[141],"expensive":[143],"SPICE":[144,153,186,196],"simulations":[145,154],"within":[146],"optimization":[148],"loop;":[149],"instead,":[150],"almost":[151],"all":[152],"confined":[156],"one-time":[159],"method":[163],"validated":[165],"variety":[168],"unseen":[170],"specifications,":[171],"solution":[175],"demonstrates":[176],"over":[177],"90%":[178],"success":[179,192],"with":[183,193],"just":[184],"one":[185],"simulation":[187],"validation,":[189],"100%":[191],"3\u20135":[194],"additional":[195],"simulations.":[197]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}