{"id":"https://openalex.org/W4410583083","doi":"https://doi.org/10.23919/date64628.2025.10992880","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","display_name":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","publication_year":2025,"publication_date":"2025-03-31","ids":{"openalex":"https://openalex.org/W4410583083","doi":"https://doi.org/10.23919/date64628.2025.10992880"},"language":"en","primary_location":{"id":"doi:10.23919/date64628.2025.10992880","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date64628.2025.10992880","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Design, Automation &amp;amp; Test in Europe Conference (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5115944819","display_name":"Navaneeth Kunhi Purayil","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Navaneeth Kunhi Purayil","raw_affiliation_strings":["ETH Z&#x00FC;rich,Z&#x00FC;rich,Switzerland"],"affiliations":[{"raw_affiliation_string":"ETH Z&#x00FC;rich,Z&#x00FC;rich,Switzerland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039942285","display_name":"Matteo Perotti","orcid":"https://orcid.org/0000-0003-2413-8592"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Matteo Perotti","raw_affiliation_strings":["ETH Z&#x00FC;rich,Z&#x00FC;rich,Switzerland"],"affiliations":[{"raw_affiliation_string":"ETH Z&#x00FC;rich,Z&#x00FC;rich,Switzerland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103019315","display_name":"Tim Fischer","orcid":"https://orcid.org/0009-0007-9700-1286"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tim Fischer","raw_affiliation_strings":["ETH Z&#x00FC;rich,Z&#x00FC;rich,Switzerland"],"affiliations":[{"raw_affiliation_string":"ETH Z&#x00FC;rich,Z&#x00FC;rich,Switzerland","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["ETH Z&#x00FC;rich,Z&#x00FC;rich,Switzerland"],"affiliations":[{"raw_affiliation_string":"ETH Z&#x00FC;rich,Z&#x00FC;rich,Switzerland","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5115944819"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":10.2326,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.98013386,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9771000146865845,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9771000146865845,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10624","display_name":"Silicon and Solar Cell Technologies","score":0.9700999855995178,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10468","display_name":"Photovoltaic System Optimization Techniques","score":0.9696000218391418,"subfield":{"id":"https://openalex.org/subfields/2105","display_name":"Renewable Energy, Sustainability and the Environment"},"field":{"id":"https://openalex.org/fields/21","display_name":"Energy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7528590559959412},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6813933253288269},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6481266617774963},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.611260712146759},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5786281824111938},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.46014297008514404},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36881300806999207},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.3668227195739746},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3384895920753479},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.15725499391555786},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14752736687660217}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7528590559959412},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6813933253288269},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6481266617774963},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.611260712146759},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5786281824111938},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.46014297008514404},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36881300806999207},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.3668227195739746},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3384895920753479},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.15725499391555786},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14752736687660217}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.23919/date64628.2025.10992880","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date64628.2025.10992880","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Design, Automation &amp;amp; Test in Europe Conference (DATE)","raw_type":"proceedings-article"},{"id":"pmh:oai:cris.unibo.it:11585/1040771","is_oa":false,"landing_page_url":"https://hdl.handle.net/11585/1040771","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5899999737739563}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W2014555481","https://openalex.org/W2144481293","https://openalex.org/W2936567838","https://openalex.org/W3102724434","https://openalex.org/W3130024571","https://openalex.org/W3178105557","https://openalex.org/W3183374399","https://openalex.org/W4311995762","https://openalex.org/W4317568852","https://openalex.org/W4387064016","https://openalex.org/W4388581261","https://openalex.org/W4388581301","https://openalex.org/W4394805411","https://openalex.org/W4394825320","https://openalex.org/W4406265948"],"related_works":["https://openalex.org/W2993622674","https://openalex.org/W2534569838","https://openalex.org/W182515070","https://openalex.org/W3116750762","https://openalex.org/W4367172762","https://openalex.org/W4364295250","https://openalex.org/W2164026451","https://openalex.org/W2900306051","https://openalex.org/W4310584696","https://openalex.org/W2036206036"],"abstract_inverted_index":{"The":[0],"ever-growing":[1],"scale":[2,70],"of":[3,55,133,158,182,195,207],"data":[4,48],"parallelism":[5],"in":[6,96,170],"today's":[7],"HPC":[8,124],"and":[9,21,35,45,58,83,103,113,125,140,150,192],"ML":[10],"applications":[11,122],"presents":[12],"a":[13,111,138,171,179,208],"big":[14],"challenge":[15,28],"for":[16,123],"computing":[17],"architectures'":[18],"energy":[19,193],"efficiency":[20,194],"performance.":[22],"Vector":[23,31,154],"processors":[24,136],"address":[25],"the":[26,39,52,62,97,129,152,163,205],"scale-up":[27],"by":[29,94,162],"decoupling":[30],"Register":[32,155],"File":[33,156],"(VRF)":[34],"datapath":[36],"widths,":[37],"allowing":[38],"VRF":[40],"to":[41,69,71,145],"host":[42],"long":[43],"vectors":[44],"increase":[46],"register-stored":[47],"reuse":[49],"while":[50],"reducing":[51],"relative":[53],"cost":[54],"instruction":[56],"fetch":[57],"decode.":[59],"However,":[60],"even":[61],"largest":[63],"vector":[64,75,88,118,135,148],"processor":[65],"designs":[66],"today":[67],"struggle":[68],"more":[72],"than":[73],"8":[74],"lanes":[76,149],"with":[77,137,202],"double-precision":[78],"Floating":[79],"Point":[80],"Units":[81],"(FPUs)":[82],"256":[84],"64-bit":[85,115],"elements":[86],"per":[87],"register.":[89],"This":[90],"limitation":[91],"is":[92],"induced":[93],"difficulties":[95],"physical":[98,130],"implementation,":[99],"which":[100],"becomes":[101],"wire-dominated":[102],"inefficient.":[104],"In":[105],"this":[106],"work,":[107],"we":[108],"present":[109],"AraXL,":[110],"modular":[112],"scalable":[114],"RISC-V":[116,164],"V":[117,165],"architecture":[119],"targeting":[120],"long-vector":[121],"ML.":[126],"AraXL":[127,177],"addresses":[128],"scalability":[131],"challenges":[132],"state-of-the-art":[134],"distributed":[139],"hierarchical":[141],"interconnect,":[142],"supporting":[143],"up":[144],"64":[146,159],"parallel":[147],"reaching":[151],"maximum":[153],"size":[157],"Kibit/vreg":[160],"permitted":[161],"1.0":[166],"ISA":[167],"specification.":[168],"Implemented":[169],"22-nm":[172],"technology":[173],"node,":[174],"our":[175],"64-lane":[176],"achieves":[178],"performance":[180],"peak":[181],"146":[183],"GFLOPs":[184],"on":[185],"computation-intensive":[186],"HPC/ML":[187],"kernels":[188],"(>99%":[189],"FPU":[190],"utilization)":[191],"40.1":[196],"GFLOPs/W":[197],"(1.15":[198],"GHz,":[199],"TT,":[200],"0.8V),":[201],"only":[203],"3.8\u00d7":[204],"area":[206],"16-lane":[209],"instance.":[210]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3}],"updated_date":"2026-03-06T13:50:29.536080","created_date":"2025-10-10T00:00:00"}
