{"id":"https://openalex.org/W4410583452","doi":"https://doi.org/10.23919/date64628.2025.10992759","title":"Three Eyed Raven: An On-Chip Side Channel Analysis Framework for Run-Time Evaluation","display_name":"Three Eyed Raven: An On-Chip Side Channel Analysis Framework for Run-Time Evaluation","publication_year":2025,"publication_date":"2025-03-31","ids":{"openalex":"https://openalex.org/W4410583452","doi":"https://doi.org/10.23919/date64628.2025.10992759"},"language":"en","primary_location":{"id":"doi:10.23919/date64628.2025.10992759","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date64628.2025.10992759","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Design, Automation & Test in Europe Conference (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5117630302","display_name":"M Dhilipkumar","orcid":null},"institutions":[{"id":"https://openalex.org/I94234084","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75","country_code":"IN","type":"education","lineage":["https://openalex.org/I94234084"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"M Dhilipkumar","raw_affiliation_strings":["Indian Institute of Technology Kanpur,Department of Computer Science & Engineering,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kanpur,Department of Computer Science & Engineering,India","institution_ids":["https://openalex.org/I94234084"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023018510","display_name":"Priyanka Bagade","orcid":"https://orcid.org/0000-0003-1045-4148"},"institutions":[{"id":"https://openalex.org/I94234084","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75","country_code":"IN","type":"education","lineage":["https://openalex.org/I94234084"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Priyanka Bagade","raw_affiliation_strings":["Indian Institute of Technology Kanpur,Department of Computer Science & Engineering,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kanpur,Department of Computer Science & Engineering,India","institution_ids":["https://openalex.org/I94234084"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102710760","display_name":"Debapriya Basu Roy","orcid":"https://orcid.org/0000-0003-4664-5237"},"institutions":[{"id":"https://openalex.org/I94234084","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75","country_code":"IN","type":"education","lineage":["https://openalex.org/I94234084"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Debapriya Basu Roy","raw_affiliation_strings":["Indian Institute of Technology Kanpur,Department of Computer Science & Engineering,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kanpur,Department of Computer Science & Engineering,India","institution_ids":["https://openalex.org/I94234084"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5117630302"],"corresponding_institution_ids":["https://openalex.org/I94234084"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12136044,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9921000003814697,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9847000241279602,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/side-channel-attack","display_name":"Side channel attack","score":0.7211298942565918},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6949756741523743},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.584876537322998},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3472130298614502},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.19047686457633972},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.17375800013542175},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.09272497892379761}],"concepts":[{"id":"https://openalex.org/C49289754","wikidata":"https://www.wikidata.org/wiki/Q2267081","display_name":"Side channel attack","level":3,"score":0.7211298942565918},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6949756741523743},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.584876537322998},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3472130298614502},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.19047686457633972},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.17375800013542175},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.09272497892379761}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date64628.2025.10992759","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date64628.2025.10992759","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Design, Automation & Test in Europe Conference (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G6105860560","display_name":null,"funder_award_id":"MEITY/CS/2024250","funder_id":"https://openalex.org/F4320325255","funder_display_name":"Ministry of Electronics and Information technology"}],"funders":[{"id":"https://openalex.org/F4320320712","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75"},{"id":"https://openalex.org/F4320325255","display_name":"Ministry of Electronics and Information technology","ror":null},{"id":"https://openalex.org/F4320334771","display_name":"Science and Engineering Research Board","ror":"https://ror.org/03ffdsr55"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2113436456","https://openalex.org/W2536656094","https://openalex.org/W2794898833","https://openalex.org/W2915743430","https://openalex.org/W2954019744","https://openalex.org/W2965942869","https://openalex.org/W2966980899","https://openalex.org/W3006293286","https://openalex.org/W3008554091","https://openalex.org/W3016064750","https://openalex.org/W3036146501","https://openalex.org/W3083028264","https://openalex.org/W3175162501","https://openalex.org/W4323310116","https://openalex.org/W6712968637","https://openalex.org/W6763074127"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W4323824501","https://openalex.org/W2355552010","https://openalex.org/W2136687465","https://openalex.org/W2390279801","https://openalex.org/W3016859066","https://openalex.org/W4391913857","https://openalex.org/W2358668433"],"abstract_inverted_index":{"Side-channel":[0],"attacks":[1],"exploit":[2],"the":[3,43,61,133,137,142,162],"physical":[4],"leakages":[5],"from":[6],"hardware":[7,77,123],"components,":[8],"such":[9,29],"as":[10],"power":[11],"consumption,":[12],"to":[13,105],"break":[14],"secure":[15],"cryptographic":[16,26,99],"algorithms":[17,27],"and":[18,46,89,128,132,144,161,168,182],"retrieve":[19],"their":[20],"secret":[21],"key.":[22],"Evaluating":[23],"implementations":[24,78,124],"of":[25,79,98,125,159,165],"against":[28],"analysis":[30],"is":[31,153],"crucial":[32],"but":[33],"traditional":[34],"frameworks":[35],"require":[36],"expensive":[37,45],"external":[38,64,113],"devices":[39,115],"like":[40],"oscilloscopes,":[41],"making":[42],"process":[44],"time-consuming.":[47],"Recent":[48],"advancements":[49],"in":[50],"on-chip":[51,57,73,103],"sensors":[52,104,138],"offer":[53],"a":[54],"cost-effective,":[55],"fully":[56],"SCA":[58,74],"framework,":[59],"eliminating":[60],"need":[62],"for":[63,95],"devices.":[65],"In":[66],"this":[67],"paper,":[68],"we":[69],"propose":[70],"Raven,":[71],"an":[72,156],"framework":[75,152],"with":[76,172],"Test":[80],"Vector":[81],"Leakage":[82,92],"Assessment":[83,93],"(TVLA),":[84],"Correlation":[85],"Power":[86],"Analysis":[87],"(CPA),":[88],"Deep":[90],"Learningbased":[91],"(DL-LA),":[94],"run-time":[96],"evaluation":[97,119],"implementations.":[100],"RAVEN":[101],"leverages":[102],"efficiently":[106],"assess":[107],"side-channel":[108],"security,":[109],"without":[110],"requiring":[111,178],"any":[112,117],"measurement":[114],"or":[116],"customized":[118],"platform.":[120,149],"Our":[121],"proposed":[122,151],"TVLA,":[126,166],"CPA,":[127,167],"DL-LA":[129,169],"are":[130],"lightweight":[131,143],"entire":[134],"architecture":[135],"including":[136],"can":[139],"fit":[140],"within":[141],"low-cost":[145],"AMD-Xilinx":[146],"PYNQ":[147],"FPGA":[148,157],"The":[150],"verified":[154],"on":[155],"implementation":[158,176],"AES-128":[160],"corresponding":[163],"result":[164],"closely":[170],"matches":[171],"these":[173],"algorithm's":[174],"software":[175],"while":[177],"significantly":[179],"less":[180],"time":[181],"storage.":[183]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}