{"id":"https://openalex.org/W4401568234","doi":"https://doi.org/10.23919/date58400.2024.10546878","title":"An Efficient Hypergraph Partitioner under Inter - Block Interconnection Constraints","display_name":"An Efficient Hypergraph Partitioner under Inter - Block Interconnection Constraints","publication_year":2024,"publication_date":"2024-03-25","ids":{"openalex":"https://openalex.org/W4401568234","doi":"https://doi.org/10.23919/date58400.2024.10546878"},"language":"en","primary_location":{"id":"doi:10.23919/date58400.2024.10546878","is_oa":false,"landing_page_url":"http://dx.doi.org/10.23919/date58400.2024.10546878","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 Design, Automation &amp;amp; Test in Europe Conference &amp;amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101613321","display_name":"Benzheng Li","orcid":"https://orcid.org/0000-0002-1227-3909"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Benzheng Li","raw_affiliation_strings":["School of Microelectronics Xidian University,Xi&#x0027;an,China"],"raw_orcid":"https://orcid.org/0000-0002-1227-3909","affiliations":[{"raw_affiliation_string":"School of Microelectronics Xidian University,Xi&#x0027;an,China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052123017","display_name":"Hailong You","orcid":"https://orcid.org/0000-0003-3427-5320"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hailong You","raw_affiliation_strings":["School of Microelectronics Xidian University,Xi&#x0027;an,China"],"raw_orcid":"https://orcid.org/0000-0003-3427-5320","affiliations":[{"raw_affiliation_string":"School of Microelectronics Xidian University,Xi&#x0027;an,China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049604762","display_name":"Shunyang Bi","orcid":"https://orcid.org/0009-0001-1341-3977"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shunyang Bi","raw_affiliation_strings":["School of Microelectronics Xidian University,Xi&#x0027;an,China"],"raw_orcid":"https://orcid.org/0009-0001-1341-3977","affiliations":[{"raw_affiliation_string":"School of Microelectronics Xidian University,Xi&#x0027;an,China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100421237","display_name":"Yuming Zhang","orcid":"https://orcid.org/0000-0002-8587-0747"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuming Zhang","raw_affiliation_strings":["School of Microelectronics Xidian University,Xi&#x0027;an,China"],"raw_orcid":"https://orcid.org/0000-0002-8587-0747","affiliations":[{"raw_affiliation_string":"School of Microelectronics Xidian University,Xi&#x0027;an,China","institution_ids":["https://openalex.org/I149594827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I149594827"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11797","display_name":"graph theory and CDMA systems","score":0.9887999892234802,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/hypergraph","display_name":"Hypergraph","score":0.895095705986023},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.8920799493789673},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7010992765426636},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.699241578578949},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5095093846321106},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.4303745925426483},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33583056926727295},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.17224431037902832},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.17054831981658936},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.10321411490440369}],"concepts":[{"id":"https://openalex.org/C2781221856","wikidata":"https://www.wikidata.org/wiki/Q840247","display_name":"Hypergraph","level":2,"score":0.895095705986023},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.8920799493789673},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7010992765426636},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.699241578578949},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5095093846321106},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.4303745925426483},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33583056926727295},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.17224431037902832},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17054831981658936},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.10321411490440369}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date58400.2024.10546878","is_oa":false,"landing_page_url":"http://dx.doi.org/10.23919/date58400.2024.10546878","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 Design, Automation &amp;amp; Test in Europe Conference &amp;amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G7767214733","display_name":null,"funder_award_id":"61574109","funder_id":"https://openalex.org/F4320327912","funder_display_name":"Higher Education Discipline Innovation Project"},{"id":"https://openalex.org/G8667409048","display_name":null,"funder_award_id":"62234010","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320327912","display_name":"Higher Education Discipline Innovation Project","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1584753249","https://openalex.org/W2023428606","https://openalex.org/W2118986737","https://openalex.org/W2120490973","https://openalex.org/W2161455936","https://openalex.org/W2402483587","https://openalex.org/W2570248857","https://openalex.org/W2998727840","https://openalex.org/W3011427649","https://openalex.org/W4200036442","https://openalex.org/W4200512355","https://openalex.org/W4226435553","https://openalex.org/W4241856644","https://openalex.org/W4242608849","https://openalex.org/W4378800754"],"related_works":["https://openalex.org/W4376608589","https://openalex.org/W1537073411","https://openalex.org/W3138003926","https://openalex.org/W1630514295","https://openalex.org/W4300037846","https://openalex.org/W4288275998","https://openalex.org/W2963081352","https://openalex.org/W4376608938","https://openalex.org/W2472555608","https://openalex.org/W2029210135"],"abstract_inverted_index":{"Multi-FPGA":[0],"systems":[1],"are":[2],"increasingly":[3],"employed":[4],"for":[5,135],"very":[6],"large":[7],"scale":[8],"integration":[9],"circuit":[10],"emulation":[11],"and":[12,42,71,119],"prototyping.":[13],"Due":[14],"to":[15,27,51,100,140],"limited":[16],"I/O":[17],"resources,":[18],"each":[19],"FPGA":[20,41,47],"often":[21],"only":[22],"has":[23],"direct":[24],"physical":[25,75],"connections":[26],"a":[28,39,45,101,113,133],"few":[29],"other":[30],"FPGAs.":[31],"Therefore,":[32],"if":[33],"signals":[34],"between":[35,81],"FPGAs":[36,56],"originate":[37],"from":[38],"source":[40,53],"flow":[43],"toward":[44],"target":[46],"not":[48],"directly":[49],"connected":[50],"the":[52,63,72,121,142,155],"FPGA,":[54],"intermediate":[55],"will":[57],"be":[58],"used":[59,77],"as":[60],"hops":[61],"in":[62,78],"signal":[64,69,79],"path.":[65],"These":[66],"FPGA-hops":[67],"increase":[68],"delays":[70],"number":[73],"of":[74,146],"lines":[76],"multiplexing":[80],"FPGAs,":[82],"degrading":[83],"system":[84],"performance.":[85],"To":[86],"address":[87],"these":[88],"issues,":[89],"researchers":[90],"proposed":[91,151],"partitioners":[92],"that":[93,149],"guarantees":[94],"zero":[95],"hop,":[96],"but":[97],"they":[98],"lead":[99],"considerable":[102],"cut-size.":[103],"In":[104],"this":[105],"paper,":[106],"building":[107],"on":[108,126],"previous":[109],"research,":[110],"we":[111,130],"introduce":[112],"new":[114],"candidate":[115],"block":[116],"propagation":[117],"theorem":[118],"optimize":[120],"initial":[122],"partition":[123],"process":[124],"based":[125],"its":[127],"corollary.":[128],"Additionally,":[129],"also":[131],"present":[132],"method":[134,152],"correcting":[136],"violations":[137],"during":[138],"uncoarsening":[139],"improve":[141],"solver":[143],"capability.":[144],"Results":[145],"experiments":[147],"demonstrate":[148],"our":[150],"significantly":[153],"reduces":[154],"cut":[156],"size":[157],"by":[158],"96%":[159],"while":[160],"retaining":[161],"comparable":[162],"running":[163],"times.":[164]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1}],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2025-10-10T00:00:00"}
