{"id":"https://openalex.org/W4401568405","doi":"https://doi.org/10.23919/date58400.2024.10546686","title":"BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0","display_name":"BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0","publication_year":2024,"publication_date":"2024-03-25","ids":{"openalex":"https://openalex.org/W4401568405","doi":"https://doi.org/10.23919/date58400.2024.10546686"},"language":"en","primary_location":{"id":"doi:10.23919/date58400.2024.10546686","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date58400.2024.10546686","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025324445","display_name":"Emad Arasteh","orcid":"https://orcid.org/0000-0003-1659-415X"},"institutions":[{"id":"https://openalex.org/I185071736","display_name":"Chapman University","ror":"https://ror.org/0452jzg20","country_code":"US","type":"education","lineage":["https://openalex.org/I185071736"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Emad M. Arasteh","raw_affiliation_strings":["Chapman University,Orange,CA,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chapman University,Orange,CA,USA","institution_ids":["https://openalex.org/I185071736"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104080209","display_name":"Vivek Govindasamy","orcid":"https://orcid.org/0009-0005-4745-3669"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vivek Govindasamy","raw_affiliation_strings":["University of California,Center for Embedded and Cyber-physical Systems,Irvine,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California,Center for Embedded and Cyber-physical Systems,Irvine,USA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111950361","display_name":"Rainer D\u00f6mer","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rainer D\u00f6mer","raw_affiliation_strings":["University of California,Center for Embedded and Cyber-physical Systems,Irvine,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California,Center for Embedded and Cyber-physical Systems,Irvine,USA","institution_ids":["https://openalex.org/I204250578"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.329,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.80178838,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9872999787330627,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9864000082015991,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9391137361526489},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.8126816749572754},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7381237745285034},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5116072297096252},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4723659157752991},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4498235583305359},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.20854908227920532}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9391137361526489},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.8126816749572754},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7381237745285034},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5116072297096252},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4723659157752991},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4498235583305359},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.20854908227920532}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date58400.2024.10546686","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date58400.2024.10546686","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1498455513","https://openalex.org/W2032669921","https://openalex.org/W2097718262","https://openalex.org/W2123345627","https://openalex.org/W2127533793","https://openalex.org/W2127746706","https://openalex.org/W2167875185","https://openalex.org/W3040708363","https://openalex.org/W3143122348","https://openalex.org/W4230022678","https://openalex.org/W4249613718","https://openalex.org/W4252622709","https://openalex.org/W4253669045","https://openalex.org/W4384339318","https://openalex.org/W6684838235"],"related_works":["https://openalex.org/W2301151507","https://openalex.org/W2170936907","https://openalex.org/W2380800843","https://openalex.org/W2140328095","https://openalex.org/W1885396597","https://openalex.org/W2105092668","https://openalex.org/W1550409889","https://openalex.org/W1830510111","https://openalex.org/W2039065447","https://openalex.org/W2208074837"],"abstract_inverted_index":{"For":[0],"designing":[1],"embedded":[2],"computer":[3],"architectures":[4],"that":[5,56,73],"meet":[6],"desired":[7],"performance":[8],"constraints":[9],"at":[10,31,60,117],"low":[11],"cost,":[12],"fast":[13],"and":[14,27,48,81,100],"accurate":[15],"simulation":[16],"models":[17],"are":[18],"needed":[19],"early":[20,30],"in":[21,85],"the":[22,32,36,75,108],"design":[23],"flow.":[24],"To":[25],"identify":[26],"avoid":[28],"bottlenecks":[29],"system":[33,61,76],"level,":[34],"observing":[35],"contention":[37,59,84],"of":[38,103,110],"shared":[39],"resources":[40],"is":[41,68],"critical.":[42],"In":[43,89],"this":[44],"paper,":[45],"we":[46],"propose":[47],"evaluate":[49],"a":[50],"novel":[51],"data":[52,71],"structure":[53,72],"called":[54],"BusyMap":[55,67,111],"accurately":[57,79],"reflects":[58],"busses":[62],"or":[63],"similar":[64],"inter-connect":[65],"components.":[66],"an":[69],"efficient":[70],"allows":[74],"designer":[77],"to":[78,91],"model":[80,95],"easily":[82],"observe":[83],"IEEE":[86],"loosely-timed":[87],"TLM-2.0.":[88],"contrast":[90],"prior":[92],"state-of-the-art,":[93],"our":[94],"fully":[96],"supports":[97],"temporal":[98],"decoupling":[99],"multiple":[101],"levels":[102],"interconnect.":[104],"Our":[105],"experiments":[106],"demonstrate":[107],"effectiveness":[109],"with":[112],"results":[113],"showing":[114],"high":[115,118],"accuracy":[116],"-speed":[119],"System":[120],"C":[121],"simulation.":[122]},"counts_by_year":[{"year":2025,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}