{"id":"https://openalex.org/W4401568221","doi":"https://doi.org/10.23919/date58400.2024.10546503","title":"An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint","display_name":"An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint","publication_year":2024,"publication_date":"2024-03-25","ids":{"openalex":"https://openalex.org/W4401568221","doi":"https://doi.org/10.23919/date58400.2024.10546503"},"language":"en","primary_location":{"id":"doi:10.23919/date58400.2024.10546503","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date58400.2024.10546503","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010781243","display_name":"Lingfeng Zhou","orcid":"https://orcid.org/0009-0006-0301-0855"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lingfeng Zhou","raw_affiliation_strings":["School of Microelectronics Science and Technology, Sun Yat-sen University,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics Science and Technology, Sun Yat-sen University,China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079537451","display_name":"Shanlin Xiao","orcid":"https://orcid.org/0000-0002-1250-8704"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shanlin Xiao","raw_affiliation_strings":["School of Microelectronics Science and Technology, Sun Yat-sen University,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics Science and Technology, Sun Yat-sen University,China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Huiyao Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Huiyao Wang","raw_affiliation_strings":["School of Microelectronics Science and Technology, Sun Yat-sen University,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics Science and Technology, Sun Yat-sen University,China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032144027","display_name":"Jinghai Wang","orcid":"https://orcid.org/0009-0006-5263-8120"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinghai Wang","raw_affiliation_strings":["School of Microelectronics Science and Technology, Sun Yat-sen University,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics Science and Technology, Sun Yat-sen University,China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103100174","display_name":"Zeyang Xu","orcid":"https://orcid.org/0009-0008-5311-1974"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zeyang Xu","raw_affiliation_strings":["School of Microelectronics Science and Technology, Sun Yat-sen University,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics Science and Technology, Sun Yat-sen University,China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002671826","display_name":"Bohan Wang","orcid":"https://orcid.org/0009-0005-6490-3203"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bohan Wang","raw_affiliation_strings":["School of Microelectronics Science and Technology, Sun Yat-sen University,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics Science and Technology, Sun Yat-sen University,China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017560036","display_name":"Zhiyi Yu","orcid":"https://orcid.org/0000-0002-8802-0457"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhiyi Yu","raw_affiliation_strings":["School of Microelectronics Science and Technology, Sun Yat-sen University,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics Science and Technology, Sun Yat-sen University,China","institution_ids":["https://openalex.org/I157773358"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I157773358"],"apc_list":null,"apc_paid":null,"fwci":1.0896,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.77348939,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9926000237464905,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9916999936103821,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6947445869445801},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6935378313064575},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.6102749705314636},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.5948725938796997},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5727311372756958},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5346863269805908},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.46655696630477905},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.4551215171813965},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3242696523666382},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.19489651918411255},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15789365768432617},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13157260417938232},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.12477970123291016},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1210097074508667},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11923977732658386},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.06917402148246765},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.06426316499710083}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6947445869445801},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6935378313064575},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.6102749705314636},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.5948725938796997},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5727311372756958},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5346863269805908},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.46655696630477905},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.4551215171813965},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3242696523666382},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.19489651918411255},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15789365768432617},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13157260417938232},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.12477970123291016},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1210097074508667},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11923977732658386},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.06917402148246765},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.06426316499710083},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date58400.2024.10546503","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date58400.2024.10546503","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7900000214576721,"display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G5158486664","display_name":null,"funder_award_id":"62334014","funder_id":"https://openalex.org/F4320320885","funder_display_name":"European Research Consortium for Informatics and Mathematics"}],"funders":[{"id":"https://openalex.org/F4320320885","display_name":"European Research Consortium for Informatics and Mathematics","ror":"https://ror.org/055zrhj18"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W122486620","https://openalex.org/W1604973310","https://openalex.org/W1932488214","https://openalex.org/W2071429830","https://openalex.org/W2487142227","https://openalex.org/W2768020033","https://openalex.org/W2783525259","https://openalex.org/W2908473507","https://openalex.org/W2978358583","https://openalex.org/W2978614371","https://openalex.org/W3015832382","https://openalex.org/W3034301158","https://openalex.org/W3088147633","https://openalex.org/W3103997615","https://openalex.org/W3207178089","https://openalex.org/W4251474723","https://openalex.org/W6683394555"],"related_works":["https://openalex.org/W4312516786","https://openalex.org/W2146990170","https://openalex.org/W2093992207","https://openalex.org/W2085028021","https://openalex.org/W1993985975","https://openalex.org/W3094139610","https://openalex.org/W2129978639","https://openalex.org/W304800142","https://openalex.org/W2388325543","https://openalex.org/W2035720669"],"abstract_inverted_index":{"Asynchronous":[0],"circuits":[1,36,53],"have":[2],"recently":[3],"become":[4],"more":[5],"popular":[6],"in":[7,44,106],"Internet":[8],"of":[9,17,28,88,108,136],"Things":[10],"(IoT)":[11],"and":[12,41,60,75,81,100,110,144],"neural":[13],"network":[14],"chips":[15],"because":[16],"their":[18],"potential":[19],"low":[20,40],"power":[21,134],"consumption.":[22],"However,":[23],"due":[24],"to":[25,84,93,127],"the":[26,34,86,96,141],"lack":[27],"Electronic":[29],"Design":[30],"Automation":[31],"(EDA)":[32],"tools,":[33,59],"asynchronous":[35,52,117,130],"design":[37,54,98],"efficiency":[38],"remains":[39],"faces":[42],"challenges":[43],"large-scale":[45],"applications.":[46],"This":[47],"paper":[48],"proposes":[49],"a":[50,62,133],"new":[51,63],"flow":[55,99],"using":[56],"traditional":[57],"EDA":[58],"applies":[61],"backward":[64],"delay":[65],"propagation":[66],"constraint":[67,101],"(BDPC)":[68],"method.":[69],"In":[70],"this":[71,114],"method,":[72],"control":[73],"paths":[74,77],"data":[76],"are":[78],"tightly":[79],"coupled":[80],"analyzed":[82],"together":[83],"improve":[85],"accuracy":[87,109],"static":[89],"timing":[90],"analysis.":[91],"Compared":[92,126],"previous":[94],"works,":[95],"proposed":[97],"method":[102],"offer":[103],"significant":[104],"advantages":[105],"terms":[107],"efficiency.":[111],"To":[112],"verify":[113],"flow,":[115],"an":[116],"RISC-V":[118],"processor":[119,131],"was":[120],"implemented":[121],"on":[122],"TSMC":[123],"65nm":[124],"process.":[125],"synchronous":[128],"version,":[129],"achieves":[132],"optimization":[135],"17.4":[137],"%":[138],"while":[139],"main-taining":[140],"same":[142],"speed":[143],"area.":[145]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2024,"cited_by_count":3}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}