{"id":"https://openalex.org/W4379115869","doi":"https://doi.org/10.23919/date56975.2023.10137211","title":"SheLL: Shrinking eFPGA Fabrics for Logic Locking","display_name":"SheLL: Shrinking eFPGA Fabrics for Logic Locking","publication_year":2023,"publication_date":"2023-04-01","ids":{"openalex":"https://openalex.org/W4379115869","doi":"https://doi.org/10.23919/date56975.2023.10137211"},"language":"en","primary_location":{"id":"doi:10.23919/date56975.2023.10137211","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date56975.2023.10137211","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020619624","display_name":"Hadi Mardani Kamali","orcid":"https://orcid.org/0000-0002-5917-5425"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hadi M Kamali","raw_affiliation_strings":["University of Florida,Department of Electrical and Computer Engineering,Gainesville,FL,USA","Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"University of Florida,Department of Electrical and Computer Engineering,Gainesville,FL,USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031747364","display_name":"Kimia Zamiri Azar","orcid":"https://orcid.org/0000-0001-5684-100X"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kimia Z Azar","raw_affiliation_strings":["University of Florida,Department of Electrical and Computer Engineering,Gainesville,FL,USA","Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"University of Florida,Department of Electrical and Computer Engineering,Gainesville,FL,USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019820972","display_name":"Farimah Farahmandi","orcid":"https://orcid.org/0000-0003-1535-0938"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Farimah Farahmandi","raw_affiliation_strings":["University of Florida,Department of Electrical and Computer Engineering,Gainesville,FL,USA","Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"University of Florida,Department of Electrical and Computer Engineering,Gainesville,FL,USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102766705","display_name":"Mark Tehranipoor","orcid":"https://orcid.org/0009-0006-8410-2347"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Tehranipoor","raw_affiliation_strings":["University of Florida,Department of Electrical and Computer Engineering,Gainesville,FL,USA","Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"University of Florida,Department of Electrical and Computer Engineering,Gainesville,FL,USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5020619624"],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":null,"apc_paid":null,"fwci":4.3059,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.95053392,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9866999983787537,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9739999771118164,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6613402366638184},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5744218230247498},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.526276171207428},{"id":"https://openalex.org/keywords/granularity","display_name":"Granularity","score":0.5256396532058716},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5222861766815186},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5202290415763855},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.481023371219635},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4409443438053131},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4292987585067749},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4271260201931},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4220377206802368},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.41176050901412964},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.411360502243042},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.41109010577201843},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2678360342979431},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1219148337841034},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09581813216209412},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.08682700991630554}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6613402366638184},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5744218230247498},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.526276171207428},{"id":"https://openalex.org/C177774035","wikidata":"https://www.wikidata.org/wiki/Q1246948","display_name":"Granularity","level":2,"score":0.5256396532058716},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5222861766815186},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5202290415763855},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.481023371219635},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4409443438053131},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4292987585067749},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4271260201931},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4220377206802368},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.41176050901412964},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.411360502243042},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.41109010577201843},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2678360342979431},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1219148337841034},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09581813216209412},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.08682700991630554},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date56975.2023.10137211","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date56975.2023.10137211","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4300000071525574,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W347636100","https://openalex.org/W1524250393","https://openalex.org/W2095410905","https://openalex.org/W2113154117","https://openalex.org/W2124954128","https://openalex.org/W2127405101","https://openalex.org/W2794385060","https://openalex.org/W2945305016","https://openalex.org/W2963001922","https://openalex.org/W2988212920","https://openalex.org/W2998465829","https://openalex.org/W3111508438","https://openalex.org/W3111808482","https://openalex.org/W3112446090","https://openalex.org/W3129912126","https://openalex.org/W3184689295","https://openalex.org/W3211638344","https://openalex.org/W3212416488","https://openalex.org/W4205241157","https://openalex.org/W4213073217","https://openalex.org/W4240172596","https://openalex.org/W4246305008","https://openalex.org/W4280495251","https://openalex.org/W6683245250","https://openalex.org/W6757041163","https://openalex.org/W6803155287"],"related_works":["https://openalex.org/W1512285683","https://openalex.org/W2151236218","https://openalex.org/W4234601000","https://openalex.org/W2139569078","https://openalex.org/W2197466303","https://openalex.org/W2187918628","https://openalex.org/W2135636985","https://openalex.org/W1607849496","https://openalex.org/W2170504327","https://openalex.org/W2526300902"],"abstract_inverted_index":{"The":[0,30,58],"utilization":[1],"of":[2,53,96,106,132],"fully":[3],"reconfigurable":[4],"logic":[5,104,123],"and":[6,15,25,99],"routing":[7],"modules":[8],"may":[9],"be":[10,39,76],"considered":[11],"as":[12,135],"one":[13,35],"potential":[14],"even":[16,70],"provably":[17],"resilient":[18],"technique":[19],"against":[20,145],"intellectual":[21],"property":[22],"(IP)":[23],"piracy":[24],"integrated":[26],"circuits":[27],"(IC)":[28],"overproduction.":[29],"embedded":[31],"FPGA":[32],"(eFPGA)":[33],"is":[34,73,118,151],"instance":[36],"that":[37,141],"could":[38],"used":[40],"for":[41,120],"IP":[42],"redaction":[43],"leading":[44],"to":[45,75,128,155],"hiding":[46],"the":[47,50,54,67,92,97,102,107,110,115,130,149,156],"functionality":[48],"through":[49],"untrusted":[51],"stages":[52],"IC":[55],"supply":[56],"chain.":[57],"eFPGA":[59,111,116,133],"architecture,":[60],"albeit":[61],"reliable,":[62],"unnecessarily":[63],"results":[64,139],"in":[65],"exploding":[66],"die":[68],"size":[69],"while":[71,148],"it":[72],"supposed":[74],"at":[77],"fine":[78],"granularity":[79],"targeting":[80],"small":[81],"modules/IPs.":[82],"In":[83,113],"this":[84,121],"paper,":[85],"we":[86],"propose":[87],"SheLL,":[88,114],"which":[89],"primarily":[90],"embeds":[91],"interconnects":[93],"(routing":[94],"channels)":[95],"design":[98,108],"secondarily":[100],"twists":[101],"minimal":[103],"parts":[105],"into":[109],"architecture.":[112],"architecture":[117],"customized":[119],"specific":[122],"locking":[124],"methodology,":[125],"allowing":[126],"us":[127],"minimize":[129],"overhead":[131,150],"fabric":[134],"possible.":[136],"Our":[137],"experimental":[138],"demonstrate":[140],"SheLL":[142],"guarantees":[143],"robustness":[144],"notable":[146],"attacks":[147],"significantly":[152],"lower":[153],"compared":[154],"existing":[157],"eFPGA-based":[158],"competitors.":[159]},"counts_by_year":[{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}