{"id":"https://openalex.org/W4379116045","doi":"https://doi.org/10.23919/date56975.2023.10137173","title":"Proteus : HLS-based NoC Generator and Simulator","display_name":"Proteus : HLS-based NoC Generator and Simulator","publication_year":2023,"publication_date":"2023-04-01","ids":{"openalex":"https://openalex.org/W4379116045","doi":"https://doi.org/10.23919/date56975.2023.10137173"},"language":"en","primary_location":{"id":"doi:10.23919/date56975.2023.10137173","is_oa":false,"landing_page_url":"http://dx.doi.org/10.23919/date56975.2023.10137173","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008320997","display_name":"Abhimanyu Rajeshkumar Bambhaniya","orcid":"https://orcid.org/0000-0003-0145-9713"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Abhimanyu Rajeshkumar Bambhaniya","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104170720","display_name":"Yangyu Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yangyu Chen","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026223175","display_name":"Anshuman","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anshuman","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052089966","display_name":"Rohan Banerjee","orcid":"https://orcid.org/0000-0001-9235-0478"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rohan Banerjee","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034089074","display_name":"Tushar Krishna","orcid":"https://orcid.org/0000-0001-5738-6942"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tushar Krishna","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5008320997"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":0.2009,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.46775267,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6798161268234253},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6488001942634583},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5298977494239807},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5147688388824463},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4823860228061676},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.46882790327072144},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4680345356464386},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.46668562293052673},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4610070586204529},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.4586501121520996},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.41262930631637573},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18257707357406616}],"concepts":[{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6798161268234253},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6488001942634583},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5298977494239807},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5147688388824463},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4823860228061676},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.46882790327072144},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4680345356464386},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.46668562293052673},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4610070586204529},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.4586501121520996},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.41262930631637573},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18257707357406616}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date56975.2023.10137173","is_oa":false,"landing_page_url":"http://dx.doi.org/10.23919/date56975.2023.10137173","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.46000000834465027,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1976878754","https://openalex.org/W1983394510","https://openalex.org/W2118231264","https://openalex.org/W2139984346","https://openalex.org/W2147657366","https://openalex.org/W2157225945","https://openalex.org/W2734326062","https://openalex.org/W2800690434","https://openalex.org/W3186375654","https://openalex.org/W4293159304"],"related_works":["https://openalex.org/W2171872191","https://openalex.org/W2129678152","https://openalex.org/W1508156141","https://openalex.org/W2057268231","https://openalex.org/W3151435834","https://openalex.org/W2001877200","https://openalex.org/W2169666835","https://openalex.org/W2124403023","https://openalex.org/W2120429086","https://openalex.org/W2059569687"],"abstract_inverted_index":{"Networks-on-chip":[0],"(NoCs)":[1],"form":[2],"the":[3,26,45,63,74,102,127,145,171,203,213],"backbone":[4],"fabric":[5],"for":[6,62],"connecting":[7],"multi-core":[8],"SoCs":[9],"containing":[10],"several":[11],"processor":[12],"cores":[13],"and":[14,60,97,118,122,158,175,189,197,232,243],"memories.":[15],"Design-space":[16],"exploration":[17],"(DSE)":[18],"of":[19,25,65,129,144,194],"NoCs":[20,139],"is":[21,41,80,126,225],"a":[22,37,116,141],"crucial":[23],"part":[24],"SoC":[27],"design":[28,104,205],"process":[29],"to":[30,72,82,89,109,133,137,165,173,201,228,237],"ensure":[31],"that":[32],"it":[33],"does":[34],"not":[35,70],"become":[36],"bottleneck.":[38],"DSE":[39,88,168],"today":[40],"often":[42],"hindered":[43],"by":[44,93,169],"inherent":[46],"trade-off":[47],"between":[48],"software":[49,157,222],"simulation":[50],"vs":[51],"hardware":[52,75,215],"emulation/e-":[53],"valuation.":[54],"Software":[55],"simulators":[56,91,231],"are":[57,69],"easily":[58],"extendable":[59],"allow":[61],"evaluation":[64,96],"new":[66],"ideas":[67],"but":[68],"able":[71],"capture":[73],"complexity.":[76],"Meanwhile,":[77],"RTL":[78,94,123,185,191],"development":[79],"known":[81],"be":[83,154],"time-consuming.":[84],"This":[85,162],"has":[86],"forced":[87],"use":[90,134],"followed":[92],"development,":[95],"feedback,":[98],"which":[99],"slows":[100],"down":[101],"overall":[103],"process.":[105],"In":[106],"an":[107],"effort":[108],"tackle":[110],"this":[111],"problem,":[112],"we":[113],"present":[114],"Proteus,":[115],"configurable":[117],"modular":[119],"NoC":[120,177,204],"simulator":[121],"generator.":[124],"Proteus":[125,224],"first":[128],"its":[130],"kind":[131],"framework":[132],"HLS":[135],"compiler":[136],"develop":[138],"from":[140],"C++":[142],"description":[143],"N":[146,151],"oC":[147],"circuit.":[148],"These":[149],"generated":[150,188],"oCs":[152],"can":[153,208],"simulated":[155],"in":[156,179,192,217],"tested":[159],"on":[160,206],"FPGAs.":[161],"allows":[163],"users":[164,234],"do":[166],"rapid":[167],"providing":[170],"opportunity":[172],"tweak":[174],"test":[176],"architectures":[178],"real-time.":[180],"We":[181],"also":[182],"compare":[183],"Proteus-generated":[184],"with":[186],"Chisel-":[187],"hand-written":[190],"terms":[193],"area,":[195],"timing":[196],"productivity.":[198],"The":[199],"ability":[200],"synthesize":[202],"FPGAs":[207],"benefit":[209],"large":[210],"designs":[211],"as":[212],"custom":[214,239],"results":[216],"faster":[218],"run-time":[219],"than":[220],"cycle-accurate":[221],"simulators.":[223],"modeled":[226],"similar":[227],"existing":[229],"state-of-the-art":[230],"offers":[233],"modifiable":[235],"parameters":[236],"generate":[238],"topologies,":[240],"routing":[241],"algorithms,":[242],"router":[244],"microarchitectures.":[245]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-12-24T23:09:58.560324","created_date":"2025-10-10T00:00:00"}
