{"id":"https://openalex.org/W4379115878","doi":"https://doi.org/10.23919/date56975.2023.10137051","title":"Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits","display_name":"Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits","publication_year":2023,"publication_date":"2023-04-01","ids":{"openalex":"https://openalex.org/W4379115878","doi":"https://doi.org/10.23919/date56975.2023.10137051"},"language":"en","primary_location":{"id":"doi:10.23919/date56975.2023.10137051","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date56975.2023.10137051","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011011809","display_name":"Tathagata Srimani","orcid":"https://orcid.org/0000-0002-1238-7324"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Tathagata Srimani","raw_affiliation_strings":["Stanford University"],"affiliations":[{"raw_affiliation_string":"Stanford University","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033289364","display_name":"Robert M. Radway","orcid":"https://orcid.org/0000-0003-3393-5489"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert M. Radway","raw_affiliation_strings":["Stanford University"],"affiliations":[{"raw_affiliation_string":"Stanford University","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100434618","display_name":"Jinwoo Kim","orcid":"https://orcid.org/0000-0003-4380-6656"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jinwoo Kim","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062937114","display_name":"Kartik Prabhu","orcid":"https://orcid.org/0000-0002-4179-1692"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kartik Prabhu","raw_affiliation_strings":["Stanford University"],"affiliations":[{"raw_affiliation_string":"Stanford University","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082730240","display_name":"D. Rich","orcid":"https://orcid.org/0000-0002-7515-1466"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dennis Rich","raw_affiliation_strings":["Stanford University"],"affiliations":[{"raw_affiliation_string":"Stanford University","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037706530","display_name":"Carlo Gilardi","orcid":"https://orcid.org/0000-0002-1883-5087"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Carlo Gilardi","raw_affiliation_strings":["Stanford University"],"affiliations":[{"raw_affiliation_string":"Stanford University","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029554261","display_name":"Priyanka Raina","orcid":"https://orcid.org/0000-0002-8834-8663"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Priyanka Raina","raw_affiliation_strings":["Stanford University"],"affiliations":[{"raw_affiliation_string":"Stanford University","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061843047","display_name":"Max M. Shulaker","orcid":"https://orcid.org/0000-0003-2237-193X"},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Max Shulaker","raw_affiliation_strings":["Massachusetts Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052950521","display_name":"Sung Kyu Lim","orcid":"https://orcid.org/0000-0002-2267-5282"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sung Kyu Lim","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036312663","display_name":"Subhasish Mitra","orcid":"https://orcid.org/0000-0002-5572-5194"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Subhasish Mitra","raw_affiliation_strings":["Stanford University"],"affiliations":[{"raw_affiliation_string":"Stanford University","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5011011809"],"corresponding_institution_ids":["https://openalex.org/I97018004"],"apc_list":null,"apc_paid":null,"fwci":0.6702,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.6792881,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/footprint","display_name":"Footprint","score":0.6404867768287659},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6372660398483276},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5903424620628357},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5644693970680237},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.501136302947998},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4383660554885864},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4343375861644745},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3553815484046936},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32636284828186035},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2716224789619446},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.223362535238266},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.177301287651062},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08421549201011658}],"concepts":[{"id":"https://openalex.org/C132943942","wikidata":"https://www.wikidata.org/wiki/Q2562511","display_name":"Footprint","level":2,"score":0.6404867768287659},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6372660398483276},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5903424620628357},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5644693970680237},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.501136302947998},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4383660554885864},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4343375861644745},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3553815484046936},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32636284828186035},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2716224789619446},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.223362535238266},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.177301287651062},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08421549201011658},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date56975.2023.10137051","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date56975.2023.10137051","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306084","display_name":"U.S. Department of Energy","ror":"https://ror.org/01bj3aw27"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1989826997","https://openalex.org/W2606722458","https://openalex.org/W2791106313","https://openalex.org/W2886146119","https://openalex.org/W2902866166","https://openalex.org/W2907909057","https://openalex.org/W2928598815","https://openalex.org/W2946670511","https://openalex.org/W2946744628","https://openalex.org/W3007788310","https://openalex.org/W3107917119","https://openalex.org/W3113040201","https://openalex.org/W3125866309","https://openalex.org/W3131920484","https://openalex.org/W3132942233","https://openalex.org/W3157657667","https://openalex.org/W3185576717","https://openalex.org/W4226187548","https://openalex.org/W4280543907","https://openalex.org/W6736288088","https://openalex.org/W6757497457","https://openalex.org/W6761177516","https://openalex.org/W6843845902"],"related_works":["https://openalex.org/W2070694218","https://openalex.org/W4253195573","https://openalex.org/W2366617252","https://openalex.org/W2017475176","https://openalex.org/W2020934033","https://openalex.org/W2143407223","https://openalex.org/W2013391748","https://openalex.org/W2092737038","https://openalex.org/W4249416173","https://openalex.org/W2977629304"],"abstract_inverted_index":{"This":[0],"paper":[1],"focuses":[2],"on":[3],"iso-on-chip-memory-capacity":[4,109],"and":[5,64,75,89,130],"iso-footprint":[6],"Energy-Delay-Product":[7],"(EDP)":[8],"benefits":[9,36,111],"of":[10,93],"ultra-dense":[11],"3D,":[12],"e.g.,":[13],"monolithic":[14],"3D":[15],"(M3D),":[16],"computing":[17],"systems":[18],"vs.":[19,121],"corresponding":[20,29,122],"2D":[21,26,123],"designs.":[22],"Simply":[23],"folding":[24],"existing":[25],"designs":[27,32,124],"into":[28,144],"M3D":[30,43,49,56,66,71,100],"physical":[31,50,67],"yields":[33],"limited":[34],"EDP":[35,57,110],"<tex":[37,114,118],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[38,115,119],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$(\\sim":[39],"1.4\\times)$</tex>":[40],".":[41],"New":[42],"architectural":[44,62,103,142,154],"design":[45,51,68,73,104,155],"points":[46,105,156],"that":[47,106,148],"exploit":[48],"are":[52],"crucial":[53],"for":[54,79],"large":[55],"benefits.":[58],"We":[59,97,134],"perform":[60],"comprehensive":[61],"exploration":[63],"detailed":[65],"using":[69],"foundry":[70],"process":[72],"kit":[74],"standard":[76],"cell":[77],"library":[78],"front-end-of-line":[80],"(FEOL)":[81],"Si":[82,128],"CMOS":[83,129],"logic,":[84],"on-chip":[85,94,131],"back-end-of-line":[86],"(BEOL)":[87],"memory,":[88],"a":[90],"single":[91],"layer":[92],"BEOL":[95,132],"FETs.":[96],"find":[98],"new":[99],"AI/ML":[101],"accelerator":[102],"have":[107],"iso-footprint,":[108],"ranging":[112],"from":[113],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$5.3\\times$</tex>":[116],"to":[117,140,152],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$11.5\\times$</tex>":[120],"(containing":[125],"only":[126],"FEOL":[127],"memory).":[133],"also":[135],"present":[136],"an":[137],"analytical":[138],"framework":[139],"derive":[141],"insights":[143],"these":[145],"benefits,":[146],"showing":[147],"our":[149],"principles":[150],"extend":[151],"many":[153],"across":[157],"various":[158],"device":[159],"technologies.":[160]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}