{"id":"https://openalex.org/W4379116049","doi":"https://doi.org/10.23919/date56975.2023.10136904","title":"High-Level Synthesis versus Hardware Construction","display_name":"High-Level Synthesis versus Hardware Construction","publication_year":2023,"publication_date":"2023-04-01","ids":{"openalex":"https://openalex.org/W4379116049","doi":"https://doi.org/10.23919/date56975.2023.10136904"},"language":"en","primary_location":{"id":"doi:10.23919/date56975.2023.10136904","is_oa":false,"landing_page_url":"http://dx.doi.org/10.23919/date56975.2023.10136904","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://research.rug.nl/en/publications/2d66bf2d-8e62-43a4-b4d6-110b2dcd1c7c","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052354481","display_name":"Alexander Kamkin","orcid":"https://orcid.org/0000-0001-6374-8575"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Alexander Kamkin","raw_affiliation_strings":["ISP RAS Plekhanov RUE MSU, MIPT, HSE"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ISP RAS Plekhanov RUE MSU, MIPT, HSE","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071221524","display_name":"Mikhail Chupilko","orcid":"https://orcid.org/0000-0002-8772-5631"},"institutions":[{"id":"https://openalex.org/I103031861","display_name":"Plekhanov Russian University of Economics","ror":"https://ror.org/04pbtsc74","country_code":"RU","type":"education","lineage":["https://openalex.org/I103031861"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Mikhail Chupilko","raw_affiliation_strings":["ISP RAS Plekhanov RUE,Moscow,Russia","ISP RAS Plekhanov RUE, Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ISP RAS Plekhanov RUE,Moscow,Russia","institution_ids":["https://openalex.org/I103031861"]},{"raw_affiliation_string":"ISP RAS Plekhanov RUE, Moscow, Russia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015447568","display_name":"M.S. Lebedev","orcid":"https://orcid.org/0000-0002-0207-7672"},"institutions":[{"id":"https://openalex.org/I103031861","display_name":"Plekhanov Russian University of Economics","ror":"https://ror.org/04pbtsc74","country_code":"RU","type":"education","lineage":["https://openalex.org/I103031861"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Mikhail Lebedev","raw_affiliation_strings":["ISP RAS Plekhanov RUE,Moscow,Russia","ISP RAS Plekhanov RUE, Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ISP RAS Plekhanov RUE,Moscow,Russia","institution_ids":["https://openalex.org/I103031861"]},{"raw_affiliation_string":"ISP RAS Plekhanov RUE, Moscow, Russia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033967187","display_name":"Sergey Smolov","orcid":"https://orcid.org/0000-0003-0173-3081"},"institutions":[{"id":"https://openalex.org/I103031861","display_name":"Plekhanov Russian University of Economics","ror":"https://ror.org/04pbtsc74","country_code":"RU","type":"education","lineage":["https://openalex.org/I103031861"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Sergey Smolov","raw_affiliation_strings":["ISP RAS Plekhanov RUE,Moscow,Russia","ISP RAS Plekhanov RUE, Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ISP RAS Plekhanov RUE,Moscow,Russia","institution_ids":["https://openalex.org/I103031861"]},{"raw_affiliation_string":"ISP RAS Plekhanov RUE, Moscow, Russia","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075050234","display_name":"Georgi Gaydadjiev","orcid":"https://orcid.org/0000-0002-3678-7007"},"institutions":[{"id":"https://openalex.org/I169381384","display_name":"University of Groningen","ror":"https://ror.org/012p63287","country_code":"NL","type":"education","lineage":["https://openalex.org/I169381384"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Georgi Gaydadjiev","raw_affiliation_strings":["University of Groningen,Plekhanov RUE,Groningen,Netherlands","Plekhanov RUE, University of Groningen, Groningen, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Groningen,Plekhanov RUE,Groningen,Netherlands","institution_ids":["https://openalex.org/I169381384"]},{"raw_affiliation_string":"Plekhanov RUE, University of Groningen, Groningen, Netherlands","institution_ids":["https://openalex.org/I169381384"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2088,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.36227462,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8116564750671387},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.8030465245246887},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.687087893486023},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6624265313148499},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6587134003639221},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.511933445930481},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.5099269151687622},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.46923428773880005},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.46706825494766235},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.46602699160575867},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4406619966030121},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.42704901099205017},{"id":"https://openalex.org/keywords/executable","display_name":"Executable","score":0.41532260179519653},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.410074383020401},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.372344046831131},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.35635197162628174},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2516096830368042}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8116564750671387},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.8030465245246887},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.687087893486023},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6624265313148499},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6587134003639221},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.511933445930481},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.5099269151687622},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.46923428773880005},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.46706825494766235},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.46602699160575867},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4406619966030121},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.42704901099205017},{"id":"https://openalex.org/C160145156","wikidata":"https://www.wikidata.org/wiki/Q778586","display_name":"Executable","level":2,"score":0.41532260179519653},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.410074383020401},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.372344046831131},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.35635197162628174},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2516096830368042},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.23919/date56975.2023.10136904","is_oa":false,"landing_page_url":"http://dx.doi.org/10.23919/date56975.2023.10136904","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.rug.nl:openaire/2d66bf2d-8e62-43a4-b4d6-110b2dcd1c7c","is_oa":true,"landing_page_url":"https://research.rug.nl/en/publications/2d66bf2d-8e62-43a4-b4d6-110b2dcd1c7c","pdf_url":null,"source":{"id":"https://openalex.org/S4306400420","display_name":"University of Groningen research database (University of Groningen / Centre for Information Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I169381384","host_organization_name":"University of Groningen","host_organization_lineage":["https://openalex.org/I169381384"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:pure.rug.nl:openaire_cris_publications/2d66bf2d-8e62-43a4-b4d6-110b2dcd1c7c","is_oa":true,"landing_page_url":"https://hdl.handle.net/11370/2d66bf2d-8e62-43a4-b4d6-110b2dcd1c7c","pdf_url":null,"source":{"id":"https://openalex.org/S4306400420","display_name":"University of Groningen research database (University of Groningen / Centre for Information Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I169381384","host_organization_name":"University of Groningen","host_organization_lineage":["https://openalex.org/I169381384"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:pure.rug.nl:openaire/2d66bf2d-8e62-43a4-b4d6-110b2dcd1c7c","is_oa":true,"landing_page_url":"https://research.rug.nl/en/publications/2d66bf2d-8e62-43a4-b4d6-110b2dcd1c7c","pdf_url":null,"source":{"id":"https://openalex.org/S4306400420","display_name":"University of Groningen research database (University of Groningen / Centre for Information Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I169381384","host_organization_name":"University of Groningen","host_organization_lineage":["https://openalex.org/I169381384"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W124174006","https://openalex.org/W391695992","https://openalex.org/W1983394510","https://openalex.org/W2030898836","https://openalex.org/W2086393337","https://openalex.org/W2095761111","https://openalex.org/W2105815873","https://openalex.org/W2156499539","https://openalex.org/W2171318521","https://openalex.org/W2343695530","https://openalex.org/W2930166203","https://openalex.org/W4235641964","https://openalex.org/W6613409409","https://openalex.org/W6683195904","https://openalex.org/W6683579492","https://openalex.org/W6761063339"],"related_works":["https://openalex.org/W2004826944","https://openalex.org/W2543290882","https://openalex.org/W1935030095","https://openalex.org/W4235515009","https://openalex.org/W2171413119","https://openalex.org/W2544421437","https://openalex.org/W2895905110","https://openalex.org/W2168113051","https://openalex.org/W2133071611","https://openalex.org/W1956832902"],"abstract_inverted_index":{"Application-specific":[0],"systems":[1],"with":[2],"FPGA":[3],"accelerators":[4],"are":[5,17,159],"often":[6],"designed":[7],"using":[8,65],"high-level":[9],"synthesis":[10],"or":[11],"hardware":[12],"construction":[13],"tools.":[14],"Nowadays,":[15],"there":[16],"many":[18],"frameworks":[19],"available,":[20],"both":[21],"open-source":[22],"and":[23,53,56,82,120,122,178,188,207,212],"commercial.":[24],"In":[25],"this":[26],"work,":[27],"we":[28,141],"aim":[29],"at":[30],"a":[31,66,75,114],"fair":[32],"comparison":[33],"of":[34,93,117,127,154,163,171],"several":[35],"languages":[36],"(and":[37],"tools),":[38],"including":[39],"Verilog":[40,46],"(our":[41],"baseline),":[42],"Chisel,":[43],"Bluespec":[44],"System":[45],"(Bluespec":[47],"Compiler),":[48],"DSLX":[49],"(XLS),":[50],"MaxJ":[51],"(MaxCompiler),":[52],"C":[54],"(Bambu":[55],"Vivado":[57],"HLS).":[58],"Our":[59,166],"analysis":[60],"has":[61],"been":[62],"carried":[63],"out":[64],"representative":[67],"example":[68],"of$8\\times":[69],"8$inverse":[70],"discrete":[71],"cosine":[72],"transform":[73],"(IDCT),":[74],"widely":[76],"used":[77,160],"algorithm":[78],"engaged":[79],"in":[80],"JPEG":[81],"MPEG":[83],"decoders.":[84],"The":[85],"metrics":[86],"under":[87],"consideration":[88],"include:":[89],"(a)":[90],"the":[91,105,118,124,146,155,184,200,203,208,217],"degree":[92],"automation":[94],"(how":[95],"much":[96],"less":[97],"code":[98,180],"is":[99,194],"required":[100],"compared":[101],"to":[102,108,130,195,198],"Verilog),":[103],"(b)":[104],"controllability":[106],"(possibility":[107],"achieve":[109,131],"given":[110,115],"design":[111,128],"characteristics,":[112],"namely":[113],"ratio":[116],"performance":[119,187,211],"area),":[121],"(c)":[123],"flexibility":[125],"(ease":[126],"modifications":[129],"certain":[132],"characteristics).":[133],"Rather":[134],"than":[135],"focusing":[136],"on":[137,183],"computational":[138,209],"kernels":[139],"only,":[140],"use":[142],"AXI-Stream":[143],"wrappers":[144],"for":[145,216,221],"synthesized":[147],"implementations,":[148],"which":[149],"allows":[150],"adequately":[151],"evaluating":[152],"characteristics":[153],"designs":[156],"when":[157],"they":[158],"as":[161],"parts":[162],"real":[164],"systems.":[165,224],"study":[167],"shows":[168],"clear":[169,214],"examples":[170],"what":[172],"impact":[173],"specific":[174],"optimizations":[175],"(tool":[176],"settings":[177],"source":[179],"modifications)":[181],"have":[182],"overall":[185],"system":[186],"area.":[189],"It":[190],"emphasizes":[191],"how":[192],"important":[193],"be":[196],"able":[197],"control":[199],"balance":[201],"between":[202],"communication":[204],"interface":[205],"utilization":[206],"kernel":[210],"delivers":[213],"guidelines":[215],"next":[218],"generation":[219],"tools":[220],"designing":[222],"FPGA-accelerator-based":[223]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}