{"id":"https://openalex.org/W4280631195","doi":"https://doi.org/10.23919/date54114.2022.9774621","title":"A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement","display_name":"A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement","publication_year":2022,"publication_date":"2022-03-14","ids":{"openalex":"https://openalex.org/W4280631195","doi":"https://doi.org/10.23919/date54114.2022.9774621"},"language":"en","primary_location":{"id":"doi:10.23919/date54114.2022.9774621","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date54114.2022.9774621","pdf_url":null,"source":{"id":"https://openalex.org/S4363607924","display_name":"2022 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006995274","display_name":"Tonmoy Dhar","orcid":"https://orcid.org/0000-0003-0980-9749"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Tonmoy Dhar","raw_affiliation_strings":["University of Minnesota,Minneapolis,MN","University of Minnesota, Minneapolis, MN"],"affiliations":[{"raw_affiliation_string":"University of Minnesota,Minneapolis,MN","institution_ids":["https://openalex.org/I130238516"]},{"raw_affiliation_string":"University of Minnesota, Minneapolis, MN","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002036272","display_name":"S Ramprasath","orcid":"https://orcid.org/0000-0001-9487-9340"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ramprasath S","raw_affiliation_strings":["University of Minnesota,Minneapolis,MN","University of Minnesota, Minneapolis, MN"],"affiliations":[{"raw_affiliation_string":"University of Minnesota,Minneapolis,MN","institution_ids":["https://openalex.org/I130238516"]},{"raw_affiliation_string":"University of Minnesota, Minneapolis, MN","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004779677","display_name":"Jitesh Poojary","orcid":"https://orcid.org/0000-0001-7548-9064"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jitesh Poojary","raw_affiliation_strings":["University of Minnesota,Minneapolis,MN","University of Minnesota, Minneapolis, MN"],"affiliations":[{"raw_affiliation_string":"University of Minnesota,Minneapolis,MN","institution_ids":["https://openalex.org/I130238516"]},{"raw_affiliation_string":"University of Minnesota, Minneapolis, MN","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055160439","display_name":"Soner Yaldiz","orcid":"https://orcid.org/0000-0002-0715-0859"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Soner Yaldiz","raw_affiliation_strings":["Intel Corporation,Hillsboro,OR","Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053468539","display_name":"Steven M. Burns","orcid":"https://orcid.org/0000-0003-0248-5403"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steven Burns","raw_affiliation_strings":["Intel Corporation,Hillsboro,OR","Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059037025","display_name":"Ramesh Harjani","orcid":"https://orcid.org/0000-0001-7691-566X"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ramesh Harjani","raw_affiliation_strings":["University of Minnesota,Minneapolis,MN","University of Minnesota, Minneapolis, MN"],"affiliations":[{"raw_affiliation_string":"University of Minnesota,Minneapolis,MN","institution_ids":["https://openalex.org/I130238516"]},{"raw_affiliation_string":"University of Minnesota, Minneapolis, MN","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068714995","display_name":"Sachin S. Sapatnekar","orcid":"https://orcid.org/0000-0002-5353-2364"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sachin S. Sapatnekar","raw_affiliation_strings":["University of Minnesota,Minneapolis,MN","University of Minnesota, Minneapolis, MN"],"affiliations":[{"raw_affiliation_string":"University of Minnesota,Minneapolis,MN","institution_ids":["https://openalex.org/I130238516"]},{"raw_affiliation_string":"University of Minnesota, Minneapolis, MN","institution_ids":["https://openalex.org/I130238516"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5006995274"],"corresponding_institution_ids":["https://openalex.org/I130238516"],"apc_list":null,"apc_paid":null,"fwci":1.2889,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.75215327,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"148","last_page":"153"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9746547937393188},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.808927059173584},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.7831122875213623},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5994240045547485},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5377588272094727},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.4715794622898102},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4520624876022339},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.42109912633895874},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.32874786853790283},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2768923342227936},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23658308386802673},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.19923993945121765},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1729724109172821}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9746547937393188},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.808927059173584},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.7831122875213623},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5994240045547485},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5377588272094727},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.4715794622898102},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4520624876022339},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.42109912633895874},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.32874786853790283},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2768923342227936},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23658308386802673},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.19923993945121765},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1729724109172821},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date54114.2022.9774621","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date54114.2022.9774621","pdf_url":null,"source":{"id":"https://openalex.org/S4363607924","display_name":"2022 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1353427963","display_name":null,"funder_award_id":"N660011824048","funder_id":"https://openalex.org/F4320337532","funder_display_name":"Space and Naval Warfare Systems Command"}],"funders":[{"id":"https://openalex.org/F4320337532","display_name":"Space and Naval Warfare Systems Command","ror":"https://ror.org/000ztjy10"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1976234067","https://openalex.org/W1996043836","https://openalex.org/W2045221862","https://openalex.org/W2108229403","https://openalex.org/W2114912418","https://openalex.org/W2121456807","https://openalex.org/W2145458600","https://openalex.org/W2503562753","https://openalex.org/W2809108639","https://openalex.org/W2945221971","https://openalex.org/W3036164688","https://openalex.org/W3036312847","https://openalex.org/W3108107800","https://openalex.org/W3110662855","https://openalex.org/W3112236443","https://openalex.org/W3113090643","https://openalex.org/W3128227371","https://openalex.org/W6752924870","https://openalex.org/W6787420830"],"related_works":["https://openalex.org/W2536880231","https://openalex.org/W2981204667","https://openalex.org/W2076615226","https://openalex.org/W2000205915","https://openalex.org/W2110634429","https://openalex.org/W1484829657","https://openalex.org/W4280631195","https://openalex.org/W2371801647","https://openalex.org/W2162372871","https://openalex.org/W3198544746"],"abstract_inverted_index":{"An":[0],"analog/mixed-signal":[1],"designer":[2],"typically":[3],"performs":[4],"circuit":[5,123],"optimization,":[6],"involving":[7],"intensive":[8],"SPICE":[9],"simulations,":[10,115],"on":[11,67,139,156],"a":[12,157,162],"schematic":[13],"netlist":[14,20],"and":[15,109,142],"then":[16],"sends":[17],"the":[18,24,60,83,122,126,130,135,151],"optimized":[19],"to":[21,30,34,39,56,133],"layout.":[22],"During":[23],"layout":[25,61],"phase,":[26],"it":[27],"is":[28,154],"vital":[29],"maintain":[31],"symmetry":[32,107],"requirements":[33],"avoid":[35,63],"performance":[36],"degradation":[37],"due":[38],"mismatch:":[40],"these":[41,88],"constraints":[42],"are":[43,117],"usually":[44],"specified":[45],"using":[46],"user":[47],"input":[48],"or":[49],"by":[50],"invoking":[51],"an":[52],"external":[53],"tool.":[54],"Moreover,":[55],"achieve":[57],"high":[58],"performance,":[59],"must":[62],"large":[64],"interconnect":[65],"parasitics":[66,74,138],"critical":[68],"nets.":[69,95],"Prior":[70],"works":[71],"that":[72],"optimize":[73],"during":[75],"placement":[76,164],"work":[77,104],"with":[78],"coarse":[79],"metrics":[80,89],"such":[81],"as":[82],"half-perimeter":[84],"wire":[85],"length,":[86],"but":[87],"do":[90],"not":[91],"appropriately":[92],"emphasize":[93,134],"performance-critical":[94,140],"The":[96,148],"novel":[97],"charge":[98],"flow":[99],"(CF)":[100],"formulation":[101],"in":[102],"this":[103],"addresses":[105],"both":[106],"detection":[108],"parasitic":[110],"optimization.":[111],"By":[112],"leveraging":[113],"schematic-level":[114],"which":[116],"available":[118],"\u201cfor":[119],"free\u201d":[120],"from":[121],"optimization":[124],"step,":[125],"approach":[127,153],"(a)":[128],"alters":[129],"objective":[131],"function":[132],"reduction":[136],"of":[137,150,159],"nets,":[141],"(b)":[143],"identifies":[144],"symmetric":[145],"elements/element":[146],"groups.":[147],"effectiveness":[149],"CF-based":[152],"demonstrated":[155],"variety":[158],"circuits":[160],"within":[161],"stochastic":[163],"engine.":[165]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
