{"id":"https://openalex.org/W4280589410","doi":"https://doi.org/10.23919/date54114.2022.9774561","title":"Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node","display_name":"Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node","publication_year":2022,"publication_date":"2022-03-14","ids":{"openalex":"https://openalex.org/W4280589410","doi":"https://doi.org/10.23919/date54114.2022.9774561"},"language":"en","primary_location":{"id":"doi:10.23919/date54114.2022.9774561","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date54114.2022.9774561","pdf_url":null,"source":{"id":"https://openalex.org/S4363607924","display_name":"2022 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073743729","display_name":"Jan Lappas","orcid":null},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Jan Lappas","raw_affiliation_strings":["Technische Universit&#x00E4;t Kaiserslautern,Germany"],"affiliations":[{"raw_affiliation_string":"Technische Universit&#x00E4;t Kaiserslautern,Germany","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073539369","display_name":"Andr\u00e9 Lucas Chinazzo","orcid":null},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Andre Chinazzo","raw_affiliation_strings":["Technische Universit&#x00E4;t Kaiserslautern,Germany"],"affiliations":[{"raw_affiliation_string":"Technische Universit&#x00E4;t Kaiserslautern,Germany","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090870819","display_name":"Christian Weis","orcid":"https://orcid.org/0000-0002-4152-0200"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Christian Weis","raw_affiliation_strings":["Technische Universit&#x00E4;t Kaiserslautern,Germany"],"affiliations":[{"raw_affiliation_string":"Technische Universit&#x00E4;t Kaiserslautern,Germany","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100568465","display_name":"Chenyang Xia","orcid":null},"institutions":[{"id":"https://openalex.org/I2250955327","display_name":"Huawei Technologies (China)","ror":"https://ror.org/00cmhce21","country_code":"CN","type":"company","lineage":["https://openalex.org/I2250955327"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chenyang Xia","raw_affiliation_strings":["Huawei Technologies Co., Ltd.,Shenzhen,China","Huawei Technologies Co., Ltd., Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"Huawei Technologies Co., Ltd.,Shenzhen,China","institution_ids":["https://openalex.org/I2250955327"]},{"raw_affiliation_string":"Huawei Technologies Co., Ltd., Shenzhen, China","institution_ids":["https://openalex.org/I2250955327"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042493542","display_name":"Zhihang Wu","orcid":"https://orcid.org/0000-0002-1948-4848"},"institutions":[{"id":"https://openalex.org/I2250955327","display_name":"Huawei Technologies (China)","ror":"https://ror.org/00cmhce21","country_code":"CN","type":"company","lineage":["https://openalex.org/I2250955327"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhihang Wu","raw_affiliation_strings":["Huawei Technologies Co., Ltd.,Shenzhen,China","Huawei Technologies Co., Ltd., Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"Huawei Technologies Co., Ltd.,Shenzhen,China","institution_ids":["https://openalex.org/I2250955327"]},{"raw_affiliation_string":"Huawei Technologies Co., Ltd., Shenzhen, China","institution_ids":["https://openalex.org/I2250955327"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030240223","display_name":"Leibin Ni","orcid":"https://orcid.org/0000-0002-5480-3146"},"institutions":[{"id":"https://openalex.org/I2250955327","display_name":"Huawei Technologies (China)","ror":"https://ror.org/00cmhce21","country_code":"CN","type":"company","lineage":["https://openalex.org/I2250955327"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Leibin Ni","raw_affiliation_strings":["Huawei Technologies Co., Ltd.,Shenzhen,China","Huawei Technologies Co., Ltd., Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"Huawei Technologies Co., Ltd.,Shenzhen,China","institution_ids":["https://openalex.org/I2250955327"]},{"raw_affiliation_string":"Huawei Technologies Co., Ltd., Shenzhen, China","institution_ids":["https://openalex.org/I2250955327"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059285190","display_name":"Norbert Wehn","orcid":"https://orcid.org/0000-0002-9010-086X"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Norbert Wehn","raw_affiliation_strings":["Technische Universit&#x00E4;t Kaiserslautern,Germany"],"affiliations":[{"raw_affiliation_string":"Technische Universit&#x00E4;t Kaiserslautern,Germany","institution_ids":["https://openalex.org/I153267046"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5073743729"],"corresponding_institution_ids":["https://openalex.org/I153267046"],"apc_list":null,"apc_paid":null,"fwci":1.6121,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.8132901,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1083","last_page":"1084"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8000373840332031},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.72719407081604},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.647395133972168},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6304307579994202},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6102339029312134},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5997779369354248},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5618741512298584},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5497022271156311},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.5007390975952148},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4911451041698456},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.48724570870399475},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.45366954803466797},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4464857578277588},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.4355645775794983},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.435322642326355},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30417004227638245},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2284996211528778},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11860013008117676}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8000373840332031},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.72719407081604},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.647395133972168},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6304307579994202},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6102339029312134},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5997779369354248},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5618741512298584},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5497022271156311},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.5007390975952148},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4911451041698456},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.48724570870399475},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.45366954803466797},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4464857578277588},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.4355645775794983},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.435322642326355},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30417004227638245},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2284996211528778},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11860013008117676},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date54114.2022.9774561","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date54114.2022.9774561","pdf_url":null,"source":{"id":"https://openalex.org/S4363607924","display_name":"2022 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W14468352","https://openalex.org/W2119985366","https://openalex.org/W2141849037","https://openalex.org/W2157555699","https://openalex.org/W2159229333","https://openalex.org/W2314747031","https://openalex.org/W2803057706","https://openalex.org/W3134526034"],"related_works":["https://openalex.org/W2050591234","https://openalex.org/W2171918386","https://openalex.org/W2594780754","https://openalex.org/W2534190481","https://openalex.org/W2991771859","https://openalex.org/W2118487491","https://openalex.org/W4285230816","https://openalex.org/W2158157809","https://openalex.org/W2139625229","https://openalex.org/W2802423915"],"abstract_inverted_index":{"With":[0],"the":[1,7,37,90,93,97,139,145],"slow-down":[2],"of":[3,44,63,87,141],"Moore's":[4],"law":[5],"and":[6,47,96,116,119,124],"increasing":[8],"requirements":[9],"on":[10,144],"energy":[11,94,122],"efficiency,":[12],"alternative":[13],"logic":[14,77,133],"styles":[15],"compared":[16,127],"to":[17,22,72,112,128],"complementary":[18,74,131],"static":[19,75],"CMOS":[20,76,132],"have":[21,109],"be":[23],"revisited":[24],"for":[25,147],"digital":[26],"circuit":[27],"implementations.":[28],"Pass":[29],"Transistor":[30],"Logic":[31],"(PTL)":[32],"gained":[33],"much":[34],"attention":[35],"in":[36],"'90s,":[38],"however,":[39],"only":[40],"a":[41,73,80,117,129],"limited":[42],"number":[43],"recent":[45,81],"investigations":[46,101],"publications":[48],"regarding":[49],"PTL":[50,66,104,149],"exist":[51],"that":[52,103],"use":[53],"advanced":[54],"technology":[55],"nodes.":[56],"This":[57],"paper":[58],"compares":[59],"key":[60],"performance":[61],"metrics":[62],"22":[64],"different":[65],"based":[67,105],"1-bit":[68],"full":[69,150],"adder":[70,106,151],"designs":[71],"reference,":[78],"using":[79],"12nm":[82],"FinFET":[83],"technology.":[84],"The":[85],"figures":[86],"merit":[88],"are":[89],"propagation":[91],"delay,":[92],"consumption,":[95],"energy-delay-product":[98],"(EDP).":[99],"Our":[100],"show":[102],"circuits":[107],"can":[108],"an":[110],"up":[111],"49%":[113],"decreased":[114],"delay":[115,146],"48%":[118],"63%":[120],"reduced":[121],"consumption":[123],"EDP,":[125],"respectively,":[126],"state-of-the-art":[130],"reference.":[134],"In":[135],"addition,":[136],"we":[137],"analyzed":[138],"impact":[140],"PVT":[142],"variations":[143],"selected":[148],"designs.":[152]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
