{"id":"https://openalex.org/W3183158071","doi":"https://doi.org/10.23919/date51398.2021.9474255","title":"ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification","display_name":"ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification","publication_year":2021,"publication_date":"2021-02-01","ids":{"openalex":"https://openalex.org/W3183158071","doi":"https://doi.org/10.23919/date51398.2021.9474255","mag":"3183158071"},"language":"en","primary_location":{"id":"doi:10.23919/date51398.2021.9474255","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date51398.2021.9474255","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049556953","display_name":"Zhen Zhuang","orcid":null},"institutions":[{"id":"https://openalex.org/I80947539","display_name":"Fuzhou University","ror":"https://ror.org/011xvna82","country_code":"CN","type":"education","lineage":["https://openalex.org/I80947539"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhen Zhuang","raw_affiliation_strings":["College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China"],"affiliations":[{"raw_affiliation_string":"College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China","institution_ids":["https://openalex.org/I80947539"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017381514","display_name":"Xing Huang","orcid":"https://orcid.org/0000-0002-5396-110X"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Xing Huang","raw_affiliation_strings":["Technical University of Munich, Munich, Bavaria, Germany"],"affiliations":[{"raw_affiliation_string":"Technical University of Munich, Munich, Bavaria, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045753829","display_name":"Genggeng Liu","orcid":"https://orcid.org/0000-0002-3099-4371"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210090176","display_name":"Institute of Computing Technology","ror":"https://ror.org/0090r4d87","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Genggeng Liu","raw_affiliation_strings":["State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210090176","https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100643723","display_name":"Wenzhong Guo","orcid":"https://orcid.org/0000-0003-4118-8823"},"institutions":[{"id":"https://openalex.org/I80947539","display_name":"Fuzhou University","ror":"https://ror.org/011xvna82","country_code":"CN","type":"education","lineage":["https://openalex.org/I80947539"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wenzhong Guo","raw_affiliation_strings":["College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China"],"affiliations":[{"raw_affiliation_string":"College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China","institution_ids":["https://openalex.org/I80947539"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036572182","display_name":"Weikang Qian","orcid":"https://orcid.org/0000-0002-5129-9431"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weikang Qian","raw_affiliation_strings":["University of Michigan-Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"University of Michigan-Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100429106","display_name":"Wenhao Liu","orcid":"https://orcid.org/0000-0001-9757-1077"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wen-Hao Liu","raw_affiliation_strings":["Block Implementation, ICD, Cadence Design Systems, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Block Implementation, ICD, Cadence Design Systems, Austin, TX, USA","institution_ids":["https://openalex.org/I66217453"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5049556953"],"corresponding_institution_ids":["https://openalex.org/I80947539"],"apc_list":null,"apc_paid":null,"fwci":0.1003,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.41930319,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1570","last_page":"1573"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.760117769241333},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7168551087379456},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.6964920163154602},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6832504272460938},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5746010541915894},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5368445515632629},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.535564124584198},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.49898791313171387},{"id":"https://openalex.org/keywords/time-division-multiplexing","display_name":"Time-division multiplexing","score":0.48453277349472046},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.4781009554862976},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.44851285219192505},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.44174426794052124},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3204226493835449},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.16536644101142883}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.760117769241333},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7168551087379456},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.6964920163154602},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6832504272460938},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5746010541915894},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5368445515632629},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.535564124584198},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.49898791313171387},{"id":"https://openalex.org/C50661577","wikidata":"https://www.wikidata.org/wiki/Q901831","display_name":"Time-division multiplexing","level":3,"score":0.48453277349472046},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.4781009554862976},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.44851285219192505},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.44174426794052124},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3204226493835449},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.16536644101142883},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date51398.2021.9474255","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date51398.2021.9474255","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7300000190734863}],"awards":[{"id":"https://openalex.org/G2193909919","display_name":null,"funder_award_id":"61877010,11501114","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1992578807","https://openalex.org/W1998679126","https://openalex.org/W2068041061","https://openalex.org/W2075490772","https://openalex.org/W2121066557","https://openalex.org/W2148658001","https://openalex.org/W2261042505","https://openalex.org/W2789489838","https://openalex.org/W2790830285","https://openalex.org/W2899799513","https://openalex.org/W2997326160","https://openalex.org/W2998727840","https://openalex.org/W3034300466","https://openalex.org/W3083156191"],"related_works":["https://openalex.org/W4244547561","https://openalex.org/W2183601056","https://openalex.org/W1996671501","https://openalex.org/W2018882851","https://openalex.org/W2371029410","https://openalex.org/W4200477342","https://openalex.org/W2258948885","https://openalex.org/W2015743564","https://openalex.org/W2156360978","https://openalex.org/W1973113362"],"abstract_inverted_index":{"As":[0,36],"the":[1,20,28,49,76,81,113,118,123],"scale":[2],"of":[3,23,30,51,87,120,129],"VLSI":[4],"circuits":[5],"increases":[6],"rapidly,":[7],"multi-FPGA":[8,130],"prototyping":[9,31,52],"systems":[10,32,131],"have":[11],"been":[12,45],"widely":[13],"used":[14],"for":[15],"logic":[16],"verification.":[17],"Due":[18],"to":[19,47,74,116],"limited":[21],"number":[22],"connections":[24],"between":[25],"FPGAs,":[26],"however,":[27],"routability":[29],"is":[33,110],"a":[34,37,57,69,106],"bottleneck.":[35],"consequence,":[38],"timing":[39],"division":[40],"multiplexing":[41,135],"(TDM)":[42],"technique":[43],"has":[44],"proposed":[46,124],"improve":[48,75,117],"usability":[50],"systems,":[53],"but":[54],"it":[55],"causes":[56],"dramatic":[58],"increase":[59],"in":[60],"system":[61,83,102],"delay.":[62,84],"In":[63],"this":[64],"paper,":[65],"we":[66],"propose":[67],"ALIFRouter,":[68],"practical":[70],"architecture-level":[71],"inter-FPGA":[72],"router,":[73],"chip":[77],"performance":[78,127],"by":[79],"reducing":[80],"corresponding":[82],"ALIFRouter":[85],"consists":[86],"three":[88,114],"major":[89,126],"stages,":[90],"including":[91],"i)":[92],"routing":[93],"topology":[94],"generation,":[95],"ii)":[96],"TDM":[97],"ratio":[98,136],"assignment,":[99],"and":[100],"iii)":[101],"delay":[103],"optimization.":[104],"Additionally,":[105],"multi-thread":[107],"parallelization":[108],"method":[109],"integrated":[111],"into":[112],"stages":[115],"efficiency":[119],"ALIFRouter.":[121],"With":[122],"algorithm,":[125],"indicators":[128],"such":[132],"as":[133],"signal":[134],"can":[137],"be":[138],"improved":[139],"significantly.":[140]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}