{"id":"https://openalex.org/W3183627489","doi":"https://doi.org/10.23919/date51398.2021.9474238","title":"Automated Synthesis of Predictable and High-Performance Cache Coherence Protocols","display_name":"Automated Synthesis of Predictable and High-Performance Cache Coherence Protocols","publication_year":2021,"publication_date":"2021-02-01","ids":{"openalex":"https://openalex.org/W3183627489","doi":"https://doi.org/10.23919/date51398.2021.9474238","mag":"3183627489"},"language":"en","primary_location":{"id":"doi:10.23919/date51398.2021.9474238","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date51398.2021.9474238","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073862711","display_name":"Anirudh Mohan Kaushik","orcid":"https://orcid.org/0000-0002-8347-0109"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Anirudh Mohan Kaushik","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Waterloo, Waterloo, Canada"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Waterloo, Waterloo, Canada","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074065388","display_name":"Hiren Patel","orcid":"https://orcid.org/0000-0003-2750-4471"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Hiren Patel","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Waterloo, Waterloo, Canada"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Waterloo, Waterloo, Canada","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5073862711"],"corresponding_institution_ids":["https://openalex.org/I151746483"],"apc_list":null,"apc_paid":null,"fwci":0.2303,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.47822657,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"816","last_page":"821"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.885738730430603},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.8590933084487915},{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.7354830503463745},{"id":"https://openalex.org/keywords/predictability","display_name":"Predictability","score":0.726498007774353},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6916790008544922},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.6078850626945496},{"id":"https://openalex.org/keywords/mesif-protocol","display_name":"MESIF protocol","score":0.5972638130187988},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.5564894676208496},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48998895287513733},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.47757795453071594},{"id":"https://openalex.org/keywords/construct","display_name":"Construct (python library)","score":0.473340779542923},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.42772701382637024},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37341317534446716},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3547685444355011},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3284169137477875},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.23935610055923462},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.22989213466644287},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.12263917922973633}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.885738730430603},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.8590933084487915},{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.7354830503463745},{"id":"https://openalex.org/C197640229","wikidata":"https://www.wikidata.org/wiki/Q2534066","display_name":"Predictability","level":2,"score":0.726498007774353},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6916790008544922},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6078850626945496},{"id":"https://openalex.org/C199979278","wikidata":"https://www.wikidata.org/wiki/Q263221","display_name":"MESIF protocol","level":5,"score":0.5972638130187988},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.5564894676208496},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48998895287513733},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.47757795453071594},{"id":"https://openalex.org/C2780801425","wikidata":"https://www.wikidata.org/wiki/Q5164392","display_name":"Construct (python library)","level":2,"score":0.473340779542923},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.42772701382637024},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37341317534446716},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3547685444355011},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3284169137477875},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.23935610055923462},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.22989213466644287},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12263917922973633},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date51398.2021.9474238","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date51398.2021.9474238","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2147657366","https://openalex.org/W2161159055","https://openalex.org/W2170293694","https://openalex.org/W2622064324","https://openalex.org/W2798867273","https://openalex.org/W2802339701","https://openalex.org/W3014248132","https://openalex.org/W3014575727","https://openalex.org/W3037030284","https://openalex.org/W6775608734","https://openalex.org/W6775669196","https://openalex.org/W6780150109"],"related_works":["https://openalex.org/W2290195868","https://openalex.org/W4285204597","https://openalex.org/W2584505417","https://openalex.org/W2140673013","https://openalex.org/W3193874149","https://openalex.org/W1555453305","https://openalex.org/W2987765027","https://openalex.org/W2352722396","https://openalex.org/W2155112318","https://openalex.org/W1499406481"],"abstract_inverted_index":{"We":[0,57,76],"present":[1],"SYNTHIA,":[2],"an":[3],"open":[4],"and":[5,11,38,43,49,55,73,81,95],"automated":[6],"tool":[7],"for":[8,18],"synthesizing":[9],"predictable":[10,37],"high-performance":[12,39],"snooping":[13],"bus-based":[14],"cache":[15,40],"coherence":[16,41],"protocols":[17,70],"multi-core":[19],"processors":[20],"in":[21,26],"multi-processor":[22],"system-on-chips":[23],"(MPSoCs)":[24],"deployed":[25],"real-time":[27],"systems.":[28],"SYNTHIA":[29,59,90],"automates":[30],"the":[31,78,85],"complex":[32],"analysis":[33],"associated":[34],"with":[35],"designing":[36],"protocols,":[42],"constructs":[44],"new":[45],"states":[46],"(transient":[47],"states)":[48],"corresponding":[50],"transitions":[51],"that":[52],"achieve":[53],"predictability":[54],"performance.":[56],"use":[58],"to":[60],"construct":[61],"complete":[62],"protocol":[63,87],"implementations":[64,88],"from":[65,89],"simple":[66],"specifications":[67],"of":[68,84],"common":[69],"(MSI,":[71],"MESI,":[72],"MOESI":[74],"protocols).":[75],"validated":[77],"correctness,":[79],"predictability,":[80],"performance":[82],"guarantees":[83],"generated":[86],"using":[91],"manually":[92],"implemented":[93],"versions,":[94],"a":[96],"micro-architectural":[97],"simulator.":[98]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
