{"id":"https://openalex.org/W3185597847","doi":"https://doi.org/10.23919/date51398.2021.9474054","title":"Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints","display_name":"Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints","publication_year":2021,"publication_date":"2021-02-01","ids":{"openalex":"https://openalex.org/W3185597847","doi":"https://doi.org/10.23919/date51398.2021.9474054","mag":"3185597847"},"language":"en","primary_location":{"id":"doi:10.23919/date51398.2021.9474054","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date51398.2021.9474054","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101664594","display_name":"Zhifeng Lin","orcid":"https://orcid.org/0000-0002-4597-4322"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhifeng Lin","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088784101","display_name":"Yanyue Xie","orcid":"https://orcid.org/0000-0002-4325-521X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yanyue Xie","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102414355","display_name":"Gang Qian","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Gang Qian","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015389986","display_name":"Chen Jianli","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jianli Chen","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084837358","display_name":"Sifei Wang","orcid":"https://orcid.org/0000-0002-7408-4118"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sifei Wang","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103098516","display_name":"Jun Yu","orcid":"https://orcid.org/0000-0003-4286-9292"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jun Yu","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5018371636","display_name":"Yao\u2010Wen Chang","orcid":"https://orcid.org/0000-0002-0564-5719"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5898,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.66035714,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1564","last_page":"1569"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.740014910697937},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6987369060516357},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5135136246681213},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4894951581954956},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.429452508687973},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.42415645718574524},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3856683671474457},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.1469942033290863},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.09686684608459473}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.740014910697937},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6987369060516357},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5135136246681213},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4894951581954956},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.429452508687973},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.42415645718574524},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3856683671474457},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.1469942033290863},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.09686684608459473}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date51398.2021.9474054","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date51398.2021.9474054","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2159119317","display_name":null,"funder_award_id":"107-2221-E-002-l61-MY3,108-2221-E-002-097-MY3","funder_id":"https://openalex.org/F4320309618","funder_display_name":"Ministry of Science and Technology"},{"id":"https://openalex.org/G506419027","display_name":null,"funder_award_id":"61977017","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G7626075271","display_name":null,"funder_award_id":"2l8YFB2202704","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"},{"id":"https://openalex.org/G7780962258","display_name":null,"funder_award_id":"107-2221-E-002-l61-MY3,108-2221-E-002-097-MY3","funder_id":"https://openalex.org/F4320317160","funder_display_name":"AnaGlobe"}],"funders":[{"id":"https://openalex.org/F4320309618","display_name":"Ministry of Science and Technology","ror":"https://ror.org/02b207r52"},{"id":"https://openalex.org/F4320317160","display_name":"AnaGlobe","ror":null},{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1983950263","https://openalex.org/W2067856828","https://openalex.org/W2094806828","https://openalex.org/W2104079056","https://openalex.org/W2108873814","https://openalex.org/W2154302973","https://openalex.org/W2533722497","https://openalex.org/W2595334824","https://openalex.org/W2596450556","https://openalex.org/W2771551340","https://openalex.org/W2774510317","https://openalex.org/W2801898382","https://openalex.org/W2886700560","https://openalex.org/W2945806107"],"related_works":["https://openalex.org/W2002703587","https://openalex.org/W3217667592","https://openalex.org/W2980006224","https://openalex.org/W2063534976","https://openalex.org/W2284838239","https://openalex.org/W3166559827","https://openalex.org/W2144122197","https://openalex.org/W2320205417","https://openalex.org/W2809345078","https://openalex.org/W3010492628"],"abstract_inverted_index":{"Modern":[0],"FPGAs":[1,42],"often":[2],"contain":[3],"heterogeneous":[4,41],"architectures":[5],"and":[6,48,55,63,83,130],"clocking":[7,100],"resources":[8],"which":[9],"must":[10],"be":[11],"considered":[12],"to":[13,43,61,78,94],"achieve":[14],"desired":[15],"solutions.":[16],"As":[17],"the":[18,81,104,109,117,126],"design":[19],"complexity":[20],"keeps":[21],"growing,":[22],"placement":[23,38,97],"has":[24],"become":[25],"critical":[26],"for":[27,40],"FPGA":[28,121],"timing":[29],"closure.":[30],"In":[31],"this":[32],"paper,":[33],"we":[34,87],"present":[35],"an":[36],"analytical":[37],"algorithm":[39,124],"optimize":[44],"its":[45],"worst":[46,128],"slack":[47,129],"clock":[49,72,82,136],"constraints":[50],"simultaneously.":[51],"First,":[52],"a":[53,70,89],"heterogeneity-aware":[54],"memory-friendly":[56],"delay":[57],"model":[58],"is":[59,76],"developed":[60],"accurately":[62],"rapidly":[64],"assess":[65],"each":[66],"connection":[67],"delay.":[68],"Then,":[69],"two-stage":[71],"region":[73],"refinement":[74],"method":[75,93],"presented":[77],"effectively":[79],"resolve":[80],"resource":[84],"violations.":[85,101],"Finally,":[86],"develop":[88],"novel":[90],"timing-based":[91],"co-optimization":[92],"generate":[95],"optimized":[96],"without":[98],"any":[99],"Compared":[102],"with":[103,116],"state-of-the-art":[105],"placer":[106],"based":[107],"on":[108],"advanced":[110],"commercial":[111],"tool":[112],"Xilinx":[113,118],"Vivado":[114],"2019.1":[115],"7":[119],"Series":[120],"architecture,":[122],"our":[123],"achieves":[125],"best":[127],"routed":[131],"wirelength":[132],"while":[133],"satisfying":[134],"all":[135],"constraints.":[137]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-03T08:13:44.112507","created_date":"2025-10-10T00:00:00"}