{"id":"https://openalex.org/W3184577234","doi":"https://doi.org/10.23919/date51398.2021.9473971","title":"Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture","display_name":"Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture","publication_year":2021,"publication_date":"2021-02-01","ids":{"openalex":"https://openalex.org/W3184577234","doi":"https://doi.org/10.23919/date51398.2021.9473971","mag":"3184577234"},"language":"en","primary_location":{"id":"doi:10.23919/date51398.2021.9473971","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date51398.2021.9473971","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102821877","display_name":"Yuge Chen","orcid":"https://orcid.org/0009-0004-3644-2203"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Yuge Chen","raw_affiliation_strings":["Department of Micro/NaNo Electronics, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Micro/NaNo Electronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062730166","display_name":"Zhongyuan Zhao","orcid":"https://orcid.org/0000-0002-6637-553X"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhongyuan Zhao","raw_affiliation_strings":["School of Electrical and Computer Engineering, Cornell University, Ithaca, NY"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Cornell University, Ithaca, NY","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008057183","display_name":"Jianfei Jiang","orcid":"https://orcid.org/0000-0002-5521-6197"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianfei Jiang","raw_affiliation_strings":["Department of Micro/NaNo Electronics, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Micro/NaNo Electronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054897331","display_name":"Guanghui He","orcid":"https://orcid.org/0000-0002-0486-6421"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guanghui He","raw_affiliation_strings":["Department of Micro/NaNo Electronics, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Micro/NaNo Electronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103236320","display_name":"Zhigang Mao","orcid":"https://orcid.org/0000-0001-9431-9853"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhigang Mao","raw_affiliation_strings":["Department of Micro/NaNo Electronics, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Micro/NaNo Electronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043703962","display_name":"Weiguang Sheng","orcid":"https://orcid.org/0000-0002-7831-526X"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weiguang Sheng","raw_affiliation_strings":["Department of Micro/NaNo Electronics, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Micro/NaNo Electronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5102821877"],"corresponding_institution_ids":["https://openalex.org/I183067930"],"apc_list":null,"apc_paid":null,"fwci":1.612,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.82581256,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"124","last_page":"129"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8739484548568726},{"id":"https://openalex.org/keywords/compile-time","display_name":"Compile time","score":0.5501372814178467},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5083691477775574},{"id":"https://openalex.org/keywords/data-access","display_name":"Data access","score":0.5036885142326355},{"id":"https://openalex.org/keywords/software-pipelining","display_name":"Software pipelining","score":0.5005614757537842},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4989476203918457},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4871087074279785},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4708150327205658},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.441177099943161},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.4258197546005249},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3574258089065552},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3209838271141052},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.29359376430511475},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.15681958198547363},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15375462174415588},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.1162666380405426}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8739484548568726},{"id":"https://openalex.org/C200833197","wikidata":"https://www.wikidata.org/wiki/Q333707","display_name":"Compile time","level":3,"score":0.5501372814178467},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5083691477775574},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.5036885142326355},{"id":"https://openalex.org/C188854837","wikidata":"https://www.wikidata.org/wiki/Q268469","display_name":"Software pipelining","level":3,"score":0.5005614757537842},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4989476203918457},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4871087074279785},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4708150327205658},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.441177099943161},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.4258197546005249},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3574258089065552},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3209838271141052},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29359376430511475},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.15681958198547363},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15375462174415588},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1162666380405426},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date51398.2021.9473971","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date51398.2021.9473971","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.9100000262260437,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W201652765","https://openalex.org/W1964191474","https://openalex.org/W1970141743","https://openalex.org/W2005873279","https://openalex.org/W2012114780","https://openalex.org/W2025787141","https://openalex.org/W2034761517","https://openalex.org/W2039974221","https://openalex.org/W2100027188","https://openalex.org/W2172296269","https://openalex.org/W2532269050","https://openalex.org/W2596494928","https://openalex.org/W2741661236","https://openalex.org/W2790925711","https://openalex.org/W2798414599","https://openalex.org/W2798862950","https://openalex.org/W2808787892","https://openalex.org/W3010420195","https://openalex.org/W3018677999","https://openalex.org/W6674943806","https://openalex.org/W6750393639","https://openalex.org/W6750668475"],"related_works":["https://openalex.org/W2389666628","https://openalex.org/W2147654880","https://openalex.org/W4241671489","https://openalex.org/W4239749048","https://openalex.org/W2149904390","https://openalex.org/W4233567673","https://openalex.org/W2764790897","https://openalex.org/W2038744993","https://openalex.org/W1554481463","https://openalex.org/W2137959138"],"abstract_inverted_index":{"Coarse-Grained":[0],"Reconfigurable":[1],"Arrays":[2],"(CGRAs)":[3],"are":[4],"promising":[5],"to":[6,57,101,147,195,207,216],"have":[7],"low":[8,149],"power":[9,47,150],"consumption":[10],"and":[11,78,138,191,238,240],"high":[12],"energy-efficiency":[13],"characteristics":[14],"as":[15],"accelerators.":[16],"Recent":[17],"years,":[18],"many":[19],"research":[20],"works":[21],"focus":[22],"on":[23,184],"improving":[24,272],"the":[25,28,32,45,49,53,70,75,90,94,103,108,118,123,130,133,148,167,176,197,209,214,218,223,230,234,242],"programmability":[26],"of":[27,39,48,52,93,132,175,179,213,233,271,277],"CGRAs":[29,41],"by":[30,88,245,274],"enabling":[31],"fast":[33],"reconfiguration":[34],"during":[35],"execution.":[36],"The":[37,153],"performance":[38,273],"these":[40,185],"critically":[42],"hinges":[43],"upon":[44],"scheduling":[46,261],"compiler.":[50],"One":[51],"critical":[54],"challenges":[55],"is":[56,116,143,158,173,269],"reduce":[58,196,217],"memory":[59,97,105,124,163,180,198,219],"access":[60,125,164,170,181],"conflicts":[61],"using":[62],"static":[63],"compilation":[64,193,262],"techniques.":[65],"Memory":[66],"accessing":[67,220],"conflict":[68,115,244],"brings":[69],"synchronization":[71],"overhead":[72],"which":[73,252],"causes":[74,122,162,178],"pipelining":[76,225],"stall":[77],"reduces":[79],"CGRA":[80,100,259,282],"performance.":[81],"Existing":[82],"compilers":[83],"usually":[84],"tackle":[85],"this":[86],"challenge":[87],"orchestrating":[89],"data":[91,134,169,211],"placement":[92],"on-chip":[95],"global":[96],"(OGM)":[98],"in":[99],"let":[102],"parallel":[104],"accesses":[106],"avoid":[107,241],"bank":[109,114,243],"conflict.":[110],"However,":[111],"we":[112,187,201,228],"find":[113],"not":[117],"only":[119],"reason":[120,160],"that":[121,161],"conflicts.":[126,165,182,199],"In":[127],"some":[128],"CGRAs,":[129],"bandwidth":[131,156,231],"network":[135,155,235],"between":[136,236],"OGM":[137,237],"processing":[139],"element":[140],"array":[141],"(PEA)":[142],"also":[144],"limited":[145],"due":[146],"design":[151],"principle.":[152],"unbalanced":[154],"loads":[157],"another":[159],"Furthermore,":[166],"redundant":[168],"across":[171],"iterations":[172],"one":[174],"primary":[177],"Based":[183],"observations,":[186],"provide":[188],"a":[189,203,247],"comprehensive":[190],"generalized":[192],"flow":[194],"Firstly,":[200],"develop":[202],"loop":[204],"transformation":[205],"model":[206],"maximize":[208],"inter-iteration":[210],"reuse":[212],"loops":[215],"operations":[221],"under":[222],"software":[224],"scheme.":[226],"Secondly,":[227],"enhance":[229],"utilization":[232],"PEA":[239],"providing":[246],"conflict-aware":[248],"spatial":[249],"mapping":[250],"algorithm":[251],"can":[253],"be":[254],"easily":[255],"integrated":[256],"into":[257],"existing":[258],"modulo":[260],"flow.":[263,284],"Experimental":[264],"results":[265],"show":[266],"our":[267],"method":[268],"capable":[270],"an":[275],"average":[276],"44%":[278],"comparing":[279],"with":[280],"state-of-the-art":[281],"compiling":[283]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
