{"id":"https://openalex.org/W3036388874","doi":"https://doi.org/10.23919/date48585.2020.9116524","title":"WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput Computation","display_name":"WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput Computation","publication_year":2020,"publication_date":"2020-03-01","ids":{"openalex":"https://openalex.org/W3036388874","doi":"https://doi.org/10.23919/date48585.2020.9116524","mag":"3036388874"},"language":"en","primary_location":{"id":"doi:10.23919/date48585.2020.9116524","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date48585.2020.9116524","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053686269","display_name":"Yehuda Kra","orcid":"https://orcid.org/0009-0002-3377-6529"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":true,"raw_author_name":"Yehuda Kra","raw_affiliation_strings":["Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076884346","display_name":"Tzachi Noy","orcid":"https://orcid.org/0000-0002-4922-5564"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Tzachi Noy","raw_affiliation_strings":["Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026444183","display_name":"Adam Teman","orcid":"https://orcid.org/0000-0002-8233-4711"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Adam Teman","raw_affiliation_strings":["Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5053686269"],"corresponding_institution_ids":["https://openalex.org/I13955877"],"apc_list":null,"apc_paid":null,"fwci":0.231,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.46152729,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"1291","last_page":"1294"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8128194212913513},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7041364908218384},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.618445634841919},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5632862448692322},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5456947684288025},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5235635638237},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5028206706047058},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.4992349147796631},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4643474221229553},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4551945924758911},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4499078392982483},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.4495750665664673},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34810543060302734},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.15869608521461487},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.1549951434135437},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.13209915161132812},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08752498030662537}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8128194212913513},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7041364908218384},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.618445634841919},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5632862448692322},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5456947684288025},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5235635638237},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5028206706047058},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.4992349147796631},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4643474221229553},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4551945924758911},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4499078392982483},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.4495750665664673},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34810543060302734},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.15869608521461487},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.1549951434135437},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.13209915161132812},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08752498030662537},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date48585.2020.9116524","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date48585.2020.9116524","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5299999713897705,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2103870427","https://openalex.org/W2137841989","https://openalex.org/W2143310750","https://openalex.org/W2153946147","https://openalex.org/W2160587268","https://openalex.org/W2163143532"],"related_works":["https://openalex.org/W2164834710","https://openalex.org/W4232019485","https://openalex.org/W2028052815","https://openalex.org/W2128528443","https://openalex.org/W2011677428","https://openalex.org/W4327499872","https://openalex.org/W2123512677","https://openalex.org/W2163318442","https://openalex.org/W2116259070","https://openalex.org/W2066822161"],"abstract_inverted_index":{"Clock-less":[0],"Wave-Propagated":[1],"Pipelining":[2],"is":[3,103],"a":[4,56,97,106,110,116],"long-known":[5],"approach":[6,31],"to":[7,19,42,95,141],"achieve":[8,142],"high-throughput":[9],"without":[10],"the":[11,70,79,128,135],"over-head":[12],"of":[13,62,72,145,154],"costly":[14],"sampling":[15],"registers.":[16],"However,":[17],"due":[18],"many":[20],"design":[21],"challenges,":[22],"which":[23,84],"have":[24],"only":[25],"increased":[26],"with":[27,86,151],"technology":[28],"scaling,":[29],"this":[30,51],"has":[32,38],"never":[33],"been":[34,40],"widely":[35],"accepted":[36],"and":[37,44,58,90,121],"generally":[39],"limited":[41],"small":[43],"very":[45],"specific":[46],"demonstrations.":[47],"This":[48],"paper":[49],"addresses":[50],"barrier":[52],"by":[53,132],"presenting":[54],"WavePro,":[55],"generic":[57],"scalable":[59],"algorithm,":[60],"capable":[61],"skew":[63,131],"balancing":[64],"any":[65],"combinatorial":[66],"logic":[67],"netlist":[68],"for":[69],"application":[71],"wave-pipelining.":[73],"The":[74,101],"algorithm":[75],"was":[76,139],"implemented":[77],"in":[78,109],"WavePro":[80],"Compiler":[81],"automation":[82],"utility,":[83],"interfaces":[85],"industry":[87],"delays":[88],"extraction":[89],"standard":[91,118],"timing":[92,123],"analysis":[93,124],"tools":[94],"produce":[96],"sign-off":[98],"quality":[99],"result.":[100],"utility":[102],"demonstrated":[104],"upon":[105],"dot-product":[107],"accelerator":[108],"65":[111],"nm":[112],"CMOS":[113],"technology,":[114],"using":[115],"vendor-provided":[117],"cell":[119],"library":[120],"commercial":[122],"tools.":[125],"By":[126],"reducing":[127],"worst-case":[129],"output":[130],"over":[133],"70%,":[134],"test":[136],"case":[137],"example":[138],"able":[140],"equivalent":[143],"throughput":[144],"an":[146],"8-staged":[147],"sequentially":[148],"pipelined":[149],"implementation":[150],"power":[152],"savings":[153],"almost":[155],"3\u00d7.":[156]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}