{"id":"https://openalex.org/W3035990767","doi":"https://doi.org/10.23919/date48585.2020.9116354","title":"Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing","display_name":"Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing","publication_year":2020,"publication_date":"2020-03-01","ids":{"openalex":"https://openalex.org/W3035990767","doi":"https://doi.org/10.23919/date48585.2020.9116354","mag":"3035990767"},"language":"en","primary_location":{"id":"doi:10.23919/date48585.2020.9116354","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date48585.2020.9116354","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035176203","display_name":"Loai Danial","orcid":"https://orcid.org/0000-0001-7539-5834"},"institutions":[{"id":"https://openalex.org/I174306211","display_name":"Technion \u2013 Israel Institute of Technology","ror":"https://ror.org/03qryx823","country_code":"IL","type":"education","lineage":["https://openalex.org/I174306211"]}],"countries":["IL"],"is_corresponding":true,"raw_author_name":"L. Danial","raw_affiliation_strings":["The Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion - Israel Institute of Technology, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"The Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion - Israel Institute of Technology, Haifa, Israel","institution_ids":["https://openalex.org/I174306211"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102012699","display_name":"V.K. Gupta","orcid":"https://orcid.org/0000-0001-9698-2800"},"institutions":[{"id":"https://openalex.org/I174306211","display_name":"Technion \u2013 Israel Institute of Technology","ror":"https://ror.org/03qryx823","country_code":"IL","type":"education","lineage":["https://openalex.org/I174306211"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"V. Gupta","raw_affiliation_strings":["The Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion - Israel Institute of Technology, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"The Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion - Israel Institute of Technology, Haifa, Israel","institution_ids":["https://openalex.org/I174306211"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082597513","display_name":"Evgeny Pikhay","orcid":"https://orcid.org/0000-0002-0156-4241"},"institutions":[{"id":"https://openalex.org/I4210109451","display_name":"Tower Semiconductor (Israel)","ror":"https://ror.org/01r2vjq11","country_code":"IL","type":"company","lineage":["https://openalex.org/I4210109451"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"E. Pikhay","raw_affiliation_strings":["TowerJazz, Migdal HaEmek, Israel"],"affiliations":[{"raw_affiliation_string":"TowerJazz, Migdal HaEmek, Israel","institution_ids":["https://openalex.org/I4210109451"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061181795","display_name":"Yakov Roizin","orcid":"https://orcid.org/0000-0002-9484-1681"},"institutions":[{"id":"https://openalex.org/I4210109451","display_name":"Tower Semiconductor (Israel)","ror":"https://ror.org/01r2vjq11","country_code":"IL","type":"company","lineage":["https://openalex.org/I4210109451"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Y. Roizin","raw_affiliation_strings":["TowerJazz, Migdal HaEmek, Israel"],"affiliations":[{"raw_affiliation_string":"TowerJazz, Migdal HaEmek, Israel","institution_ids":["https://openalex.org/I4210109451"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014138496","display_name":"Shahar Kvatinsky","orcid":"https://orcid.org/0000-0001-7277-7271"},"institutions":[{"id":"https://openalex.org/I174306211","display_name":"Technion \u2013 Israel Institute of Technology","ror":"https://ror.org/03qryx823","country_code":"IL","type":"education","lineage":["https://openalex.org/I174306211"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"S. Kvatinsky","raw_affiliation_strings":["The Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion - Israel Institute of Technology, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"The Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion - Israel Institute of Technology, Haifa, Israel","institution_ids":["https://openalex.org/I174306211"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5035176203"],"corresponding_institution_ids":["https://openalex.org/I174306211"],"apc_list":null,"apc_paid":null,"fwci":0.5137,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.64213038,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"472","last_page":"477"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10581","display_name":"Neural dynamics and brain function","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2805","display_name":"Cognitive Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/neuromorphic-engineering","display_name":"Neuromorphic engineering","score":0.9368022680282593},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6440075635910034},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.5866005420684814},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5628906488418579},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4697927236557007},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46650972962379456},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4581640362739563},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4236077666282654},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.41679248213768005},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33140599727630615},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.2745230495929718},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26531368494033813},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18838420510292053},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.15167397260665894},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.149160236120224},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09203675389289856}],"concepts":[{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.9368022680282593},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6440075635910034},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.5866005420684814},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5628906488418579},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4697927236557007},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46650972962379456},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4581640362739563},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4236077666282654},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.41679248213768005},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33140599727630615},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.2745230495929718},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26531368494033813},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18838420510292053},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.15167397260665894},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.149160236120224},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09203675389289856},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date48585.2020.9116354","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date48585.2020.9116354","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1542981317","https://openalex.org/W1578783943","https://openalex.org/W1964175594","https://openalex.org/W1989221929","https://openalex.org/W2030671441","https://openalex.org/W2047552062","https://openalex.org/W2112166600","https://openalex.org/W2112181056","https://openalex.org/W2134682148","https://openalex.org/W2143483829","https://openalex.org/W2162651880","https://openalex.org/W2163630896","https://openalex.org/W2198142417","https://openalex.org/W2532239183","https://openalex.org/W2777126322","https://openalex.org/W2778345336","https://openalex.org/W2992817139","https://openalex.org/W4388323961","https://openalex.org/W6679767691"],"related_works":["https://openalex.org/W4381329097","https://openalex.org/W4293054835","https://openalex.org/W2946103847","https://openalex.org/W2108396330","https://openalex.org/W2061181929","https://openalex.org/W2584544613","https://openalex.org/W2303515603","https://openalex.org/W1817913304","https://openalex.org/W3021792483","https://openalex.org/W2245173025"],"abstract_inverted_index":{"Memristive":[0],"technology":[1],"is":[2],"still":[3,37],"not":[4],"mature":[5],"enough":[6],"for":[7],"the":[8,43,53,57,61,65,84],"very":[9,29],"large-scale":[10,30],"integration":[11],"necessary":[12],"to":[13],"obtain":[14],"practical":[15],"value":[16],"from":[17],"neuromorphic":[18,32,93],"computing.":[19,94],"While":[20],"nonvolatile":[21],"floating-gate":[22,48,58,85],"\"synapse":[23],"transistors\"":[24],"have":[25],"been":[26],"implemented":[27],"in":[28,92],"integrated":[31],"systems,":[33],"their":[34],"large":[35],"footprint":[36],"constrains":[38],"an":[39],"upper":[40],"bound":[41],"on":[42],"overall":[44],"performance.":[45],"A":[46],"two-terminal":[47],"memristive":[49,86],"device":[50,87],"can":[51],"combine":[52],"technological":[54],"maturity":[55],"of":[56,64,83],"transistor":[59],"and":[60,88,111],"conceptual":[62],"novelty":[63],"memristor":[66],"using":[67],"a":[68,77,98,103],"standard":[69],"CMOS":[70],"process.":[71],"In":[72],"this":[73],"paper,":[74],"we":[75],"present":[76],"top-down":[78],"computer":[79],"aided":[80],"design":[81],"framework":[82,96],"show":[89],"its":[90],"potential":[91],"Our":[95],"includes":[97],"Verilog-A":[99],"model,":[100,105],"small-signal":[101],"schematics,":[102],"stochastic":[104],"Monte-Carlo":[106],"simulations,":[107],"layout,":[108],"DRC,":[109],"LVS,":[110],"RC":[112],"extraction.":[113]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
