{"id":"https://openalex.org/W3036444874","doi":"https://doi.org/10.23919/date48585.2020.9116313","title":"Towards Serial-Equivalent Multi-Core Parallel Routing for FPGAs","display_name":"Towards Serial-Equivalent Multi-Core Parallel Routing for FPGAs","publication_year":2020,"publication_date":"2020-03-01","ids":{"openalex":"https://openalex.org/W3036444874","doi":"https://doi.org/10.23919/date48585.2020.9116313","mag":"3036444874"},"language":"en","primary_location":{"id":"doi:10.23919/date48585.2020.9116313","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date48585.2020.9116313","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002840650","display_name":"Minghua Shen","orcid":"https://orcid.org/0000-0003-4747-8020"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Minghua Shen","raw_affiliation_strings":["School of Data and Computer Science, Sun Yat-sen University, Guangzhou, China"],"affiliations":[{"raw_affiliation_string":"School of Data and Computer Science, Sun Yat-sen University, Guangzhou, China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023506057","display_name":"Nong Xiao","orcid":"https://orcid.org/0000-0002-2166-977X"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Nong Xiao","raw_affiliation_strings":["School of Data and Computer Science, Sun Yat-sen University, Guangzhou, China"],"affiliations":[{"raw_affiliation_string":"School of Data and Computer Science, Sun Yat-sen University, Guangzhou, China","institution_ids":["https://openalex.org/I157773358"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5002840650"],"corresponding_institution_ids":["https://openalex.org/I157773358"],"apc_list":null,"apc_paid":null,"fwci":0.1542,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.5032898,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"1139","last_page":"1144"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.8695247173309326},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7986067533493042},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7868956327438354},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.679250180721283},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6013043522834778},{"id":"https://openalex.org/keywords/queue","display_name":"Queue","score":0.5885342359542847},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5387258529663086},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.5296924710273743},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.499373197555542},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.45458707213401794},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.23477381467819214},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23183801770210266},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0951460599899292}],"concepts":[{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.8695247173309326},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7986067533493042},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7868956327438354},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.679250180721283},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6013043522834778},{"id":"https://openalex.org/C160403385","wikidata":"https://www.wikidata.org/wiki/Q220543","display_name":"Queue","level":2,"score":0.5885342359542847},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5387258529663086},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.5296924710273743},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.499373197555542},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.45458707213401794},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.23477381467819214},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23183801770210266},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0951460599899292},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date48585.2020.9116313","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date48585.2020.9116313","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1931688030","https://openalex.org/W2005602803","https://openalex.org/W2023428606","https://openalex.org/W2038935766","https://openalex.org/W2076857855","https://openalex.org/W2105917387","https://openalex.org/W2124710458","https://openalex.org/W2156041594","https://openalex.org/W2171768221","https://openalex.org/W2275304190","https://openalex.org/W2774839901","https://openalex.org/W2792745633","https://openalex.org/W2945848132","https://openalex.org/W4233693404","https://openalex.org/W4249043400","https://openalex.org/W6640260113"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2013643406","https://openalex.org/W2027972911","https://openalex.org/W2157978810","https://openalex.org/W2597809628","https://openalex.org/W3012895752"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"present":[4],"a":[5,32,66,82],"serial-equivalent":[6],"parallel":[7,57,97,104,123],"router":[8,25,105,124,133],"for":[9,65,81],"FPGAs":[10],"on":[11,18,62,110],"modern":[12],"multi-core":[13,63,96],"processors.":[14],"We":[15,54,69],"are":[16,40,49],"based":[17],"the":[19,29,37,46,56,71,95,118,127,131],"inherent":[20],"net":[21],"order":[22],"of":[23,34,59,74],"serial":[24,119,132,135],"to":[26,93,117],"schedule":[27],"all":[28],"nets":[30,39,48,61],"into":[31],"series":[33],"stages,":[35],"where":[36],"non-conflicting":[38,60],"scheduled":[41,50],"in":[42,51],"same":[43,128],"stage":[44],"and":[45],"conflicting":[47,75],"different":[52],"stages.":[53],"explore":[55],"routing":[58,84],"processors":[64],"significant":[67],"speedup.":[68],"perform":[70],"data":[72],"synchronization":[73],"stages":[76],"using":[77,112],"MPI-based":[78],"message":[79],"queue":[80],"feasible":[83],"solution.":[85],"Note":[86],"that":[87,102],"load":[88],"balance":[89],"is":[90],"always":[91],"used":[92],"guide":[94],"routing.":[98],"Experimental":[99],"results":[100],"show":[101],"our":[103,122],"provides":[106],"about":[107],"19.13\u00d7":[108],"speedup":[109],"average":[111],"32":[113],"processor":[114],"cores":[115],"comparing":[116],"router.":[120],"Notably,":[121],"generates":[125],"exactly":[126],"wirelength":[129],"as":[130],"satisfying":[134],"equivalency.":[136]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}