{"id":"https://openalex.org/W3036033727","doi":"https://doi.org/10.23919/date48585.2020.9116309","title":"Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization","display_name":"Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization","publication_year":2020,"publication_date":"2020-03-01","ids":{"openalex":"https://openalex.org/W3036033727","doi":"https://doi.org/10.23919/date48585.2020.9116309","mag":"3036033727"},"language":"en","primary_location":{"id":"doi:10.23919/date48585.2020.9116309","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date48585.2020.9116309","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100338343","display_name":"Zi Wang","orcid":"https://orcid.org/0000-0003-3197-2550"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Zi Wang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Dallas"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Dallas","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032819369","display_name":"Jianqi Chen","orcid":"https://orcid.org/0000-0003-0031-8417"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jianqi Chen","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Dallas"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Dallas","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110952529","display_name":"Benjamin Carrion Schafer","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Benjamin Carrion Schafer","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Dallas"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Dallas","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100338343"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":1.874,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.85477237,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"145","last_page":"150"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10260","display_name":"Software Engineering Research","score":0.989300012588501,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9879000186920166,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7265229821205139},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6925051212310791},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6479624509811401},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5220137238502502},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.45073217153549194},{"id":"https://openalex.org/keywords/pareto-principle","display_name":"Pareto principle","score":0.41522300243377686},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4141644537448883},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37486064434051514},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24794667959213257},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.24714839458465576},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.18010342121124268},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13717257976531982},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10495319962501526}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7265229821205139},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6925051212310791},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6479624509811401},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5220137238502502},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.45073217153549194},{"id":"https://openalex.org/C137635306","wikidata":"https://www.wikidata.org/wiki/Q182667","display_name":"Pareto principle","level":2,"score":0.41522300243377686},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4141644537448883},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37486064434051514},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24794667959213257},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.24714839458465576},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.18010342121124268},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13717257976531982},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10495319962501526},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date48585.2020.9116309","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date48585.2020.9116309","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1490783972","https://openalex.org/W1647732624","https://openalex.org/W1976471683","https://openalex.org/W2034270503","https://openalex.org/W2038985591","https://openalex.org/W2039856364","https://openalex.org/W2041183895","https://openalex.org/W2109672848","https://openalex.org/W2113234488","https://openalex.org/W2138209363","https://openalex.org/W2145600257","https://openalex.org/W2156499539","https://openalex.org/W2345438070","https://openalex.org/W2398354748","https://openalex.org/W2482246557","https://openalex.org/W2619340758","https://openalex.org/W2757637133","https://openalex.org/W2774970068","https://openalex.org/W2782904295","https://openalex.org/W2808879374","https://openalex.org/W2911122160","https://openalex.org/W2975468520","https://openalex.org/W3100932218","https://openalex.org/W4229673714","https://openalex.org/W4237292617","https://openalex.org/W4242789686","https://openalex.org/W6660970551","https://openalex.org/W6677096686","https://openalex.org/W6683195904","https://openalex.org/W6748111074"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W2269990635","https://openalex.org/W4312985392","https://openalex.org/W4283730710","https://openalex.org/W2042762783","https://openalex.org/W4281784598","https://openalex.org/W2921149022","https://openalex.org/W2108242004","https://openalex.org/W4313484792","https://openalex.org/W4282568311"],"abstract_inverted_index":{"This":[0,41,64],"work":[1],"proposes":[2],"a":[3,86,155],"method":[4,132,195],"to":[5,29,67,83,117,125,153,171,182],"accelerate":[6],"the":[7,36,53,62,97,103,109,119,126,136,147,151,177,186],"process":[8],"of":[9,25,33,49,79,105,112,138,146,168,198],"High-Level":[10],"Synthesis":[11],"(HLS)":[12],"Design":[13],"Space":[14],"Exploration":[15],"(DSE)":[16],"by":[17,45],"pre-characterizing":[18],"micro-kernels":[19,139,175,179],"offline":[20],"and":[21,75,149],"creating":[22,141],"predictive":[23,142],"models":[24,143],"these.":[26],"HLS":[27,114],"allows":[28],"generate":[30],"different":[31,47],"types":[32],"micro-architectures":[34,84],"from":[35],"same":[37],"untimed":[38],"behavioral":[39,158],"description.":[40],"is":[42,95,116,133,196],"typically":[43],"done":[44],"setting":[46],"combinations":[48,78,122],"synthesis":[50,56,120],"options":[51],"in":[52,61,180],"form":[54],"or":[55],"directives":[57],"specified":[58],"as":[59],"pragmas":[60,81],"code.":[63],"allows,":[65],"e.g.":[66],"control":[68],"how":[69],"loops":[70],"should":[71],"be":[72],"synthesized,":[73],"arrays":[74],"functions.":[76],"Unique":[77],"these":[80],"leads":[82],"with":[85,102,176],"unique":[87],"area":[88],"vs.":[89],"performance/power":[90],"trade-offs.":[91],"The":[92],"main":[93,110],"problem":[94],"that":[96,123,192],"search":[98,187],"space":[99],"grows":[100],"exponentially":[101],"number":[104],"explorable":[106],"operations.":[107],"Thus,":[108],"goal":[111],"efficient":[113],"DSE":[115],"find":[118],"directives'":[121],"lead":[124],"Pareto-optimal":[127],"designs":[128],"quickly.":[129],"Our":[130],"proposed":[131,194],"based":[134],"on":[135],"pre-characterization":[137],"offline,":[140],"for":[144],"each":[145],"kernels,":[148],"using":[150,160],"results":[152,190],"explore":[154],"new":[156,173],"unseen":[157,174],"description":[159],"compositional":[161],"methods.":[162,203],"In":[163],"addition,":[164],"we":[165],"make":[166],"use":[167],"perceptual":[169],"hashing":[170],"match":[172],"pre-characterized":[178],"order":[181],"further":[183],"speed":[184],"up":[185],"process.":[188],"Experimental":[189],"show":[191],"our":[193],"orders":[197],"magnitude":[199],"faster":[200],"than":[201],"traditional":[202]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":1}],"updated_date":"2026-03-13T16:22:10.518609","created_date":"2025-10-10T00:00:00"}
