{"id":"https://openalex.org/W2946427270","doi":"https://doi.org/10.23919/date.2019.8715096","title":"Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI","display_name":"Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI","publication_year":2019,"publication_date":"2019-03-01","ids":{"openalex":"https://openalex.org/W2946427270","doi":"https://doi.org/10.23919/date.2019.8715096","mag":"2946427270"},"language":"en","primary_location":{"id":"doi:10.23919/date.2019.8715096","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2019.8715096","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074654905","display_name":"Sun ik Heo","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Sun ik Heo","raw_affiliation_strings":["Samsung Electronics Co., Ltd., Hwaseong-si, Gyeonggi-do, South Korea"],"affiliations":[{"raw_affiliation_string":"Samsung Electronics Co., Ltd., Hwaseong-si, Gyeonggi-do, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073558386","display_name":"Andrew B. Kahng","orcid":"https://orcid.org/0000-0002-4490-5018"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Andrew B. Kahng","raw_affiliation_strings":["CSE, La Jolla, CA, USA"],"affiliations":[{"raw_affiliation_string":"CSE, La Jolla, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100362669","display_name":"Minsoo Kim","orcid":"https://orcid.org/0000-0002-6488-4349"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Minsoo Kim","raw_affiliation_strings":["ECE Departments, UC San Diego, La Jolla, CA, USA"],"affiliations":[{"raw_affiliation_string":"ECE Departments, UC San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051578140","display_name":"Lutong Wang","orcid":"https://orcid.org/0000-0003-3702-5095"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lutong Wang","raw_affiliation_strings":["ECE Departments, UC San Diego, La Jolla, CA, USA"],"affiliations":[{"raw_affiliation_string":"ECE Departments, UC San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017431067","display_name":"Chutong Yang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chutong Yang","raw_affiliation_strings":["CSE, La Jolla, CA, USA"],"affiliations":[{"raw_affiliation_string":"CSE, La Jolla, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5074654905"],"corresponding_institution_ids":["https://openalex.org/I2250650973"],"apc_list":null,"apc_paid":null,"fwci":1.55,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":{"value":0.83273511,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"830","last_page":"835"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7389563322067261},{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.5609524846076965},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5506722331047058},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5041238069534302},{"id":"https://openalex.org/keywords/drop","display_name":"Drop (telecommunication)","score":0.4803718030452728},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4199592173099518},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3612787127494812},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.33183932304382324},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3269180655479431},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3174273371696472},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2717796564102173},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12034884095191956},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.0820637047290802}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7389563322067261},{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.5609524846076965},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5506722331047058},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5041238069534302},{"id":"https://openalex.org/C2781345722","wikidata":"https://www.wikidata.org/wiki/Q5308388","display_name":"Drop (telecommunication)","level":2,"score":0.4803718030452728},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4199592173099518},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3612787127494812},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.33183932304382324},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3269180655479431},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3174273371696472},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2717796564102173},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12034884095191956},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0820637047290802},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date.2019.8715096","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2019.8715096","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320332603","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2103833707","https://openalex.org/W2116319078","https://openalex.org/W2149363078","https://openalex.org/W2595225635","https://openalex.org/W2751111909","https://openalex.org/W4245622810","https://openalex.org/W4253179139","https://openalex.org/W6734649425","https://openalex.org/W6743386225"],"related_works":["https://openalex.org/W4205718258","https://openalex.org/W2059364457","https://openalex.org/W1989674257","https://openalex.org/W4233629644","https://openalex.org/W2109799272","https://openalex.org/W1987230547","https://openalex.org/W4283721994","https://openalex.org/W2319035808","https://openalex.org/W184298953","https://openalex.org/W3014070231"],"abstract_inverted_index":{"Power":[0],"Delivery":[1],"Network":[2],"(PDN)":[3],"is":[4],"one":[5],"of":[6,22,63,104],"the":[7,61,88,102,108],"most":[8],"challenging":[9],"topics":[10],"in":[11,28,48,92,120],"modern":[12],"VLSI":[13],"design.":[14],"Due":[15],"to":[16,51,86,100,107,115],"aggressive":[17],"technology":[18],"node":[19],"scaling,":[20],"resistance":[21],"back-end-of-line":[23],"(BEOL)":[24],"layers":[25,50],"increases":[26],"dramatically":[27],"sub-10nm":[29],"VLSI,":[30],"causing":[31],"high":[32],"supply":[33],"voltage":[34],"(IR)":[35],"drop.":[36],"To":[37],"solve":[38],"this":[39,74],"problem,":[40],"pre-placed":[41],"or":[42,67],"post-placed":[43],"power":[44,54,69,89],"staples":[45],"are":[46],"inserted":[47],"pin-access":[49],"connect":[52],"adjacent":[53],"rails":[55],"and":[56,81],"reduce":[57],"PDN":[58],"resistance,":[59],"at":[60],"cost":[62],"reduced":[64,68],"routing":[65],"flexibility,":[66],"staple":[70,90],"insertion":[71,91],"opportunity.":[72],"In":[73],"work,":[75],"we":[76,112],"propose":[77,98],"dynamic":[78],"programming-based":[79],"single-row":[80],"double-row":[82],"detailed":[83],"placement":[84],"optimizations":[85],"maximize":[87],"a":[93],"post-placement":[94,110],"flow.":[95],"We":[96],"further":[97],"metaheuristics":[99],"improve":[101],"quality":[103],"result.":[105],"Compared":[106],"traditional":[109],"flow,":[111],"achieve":[113],"up":[114],"13.2%":[116],"(10mV":[117],")":[118],"reduction":[119],"IR":[121],"drop,":[122],"with":[123],"almost":[124],"no":[125],"WNS":[126],"degradation.":[127]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}