{"id":"https://openalex.org/W2946637109","doi":"https://doi.org/10.23919/date.2019.8714992","title":"An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel","display_name":"An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel","publication_year":2019,"publication_date":"2019-03-01","ids":{"openalex":"https://openalex.org/W2946637109","doi":"https://doi.org/10.23919/date.2019.8714992","mag":"2946637109"},"language":"en","primary_location":{"id":"doi:10.23919/date.2019.8714992","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2019.8714992","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102790446","display_name":"Xin Wei","orcid":"https://orcid.org/0000-0003-1138-441X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xin Wei","raw_affiliation_strings":["State Key Lab of ASIC and System, Fudan University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037328458","display_name":"Changhao Yan","orcid":"https://orcid.org/0000-0002-8936-3945"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Changhao Yan","raw_affiliation_strings":["State Key Lab of ASIC and System, Fudan University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052779900","display_name":"Hai Zhou","orcid":"https://orcid.org/0000-0002-0869-3038"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hai Zhou","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Northwestern University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Northwestern University, USA","institution_ids":["https://openalex.org/I111979921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054960059","display_name":"Dian Zhou","orcid":"https://orcid.org/0000-0002-2648-5232"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dian Zhou","raw_affiliation_strings":["State Key Lab of ASIC and System, Fudan University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064213921","display_name":"Xuan Zeng","orcid":"https://orcid.org/0000-0002-8097-4053"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuan Zeng","raw_affiliation_strings":["State Key Lab of ASIC and System, Fudan University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1040","last_page":"1045"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9937999844551086,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7854406833648682},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7533975839614868},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5723411440849304},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.47906169295310974},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.4366767108440399},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3972257673740387},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3429049551486969},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09810453653335571}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7854406833648682},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7533975839614868},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5723411440849304},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.47906169295310974},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.4366767108440399},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3972257673740387},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3429049551486969},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09810453653335571},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date.2019.8714992","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2019.8714992","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1635446386","https://openalex.org/W1997312881","https://openalex.org/W2041506790","https://openalex.org/W2096636123","https://openalex.org/W2122845573","https://openalex.org/W2152428313","https://openalex.org/W2157089032","https://openalex.org/W2159860184","https://openalex.org/W2520083297","https://openalex.org/W2728213123","https://openalex.org/W2740087560","https://openalex.org/W2763326469","https://openalex.org/W4255003042"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W4401278057","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841"],"abstract_inverted_index":{"The":[0,98,179],"floating":[1],"random":[2,93],"walk":[3],"(FRW)":[4],"algorithm":[5,122,149],"is":[6,130,152,162],"an":[7,211],"important":[8],"method":[9],"widely":[10],"used":[11,140],"in":[12],"the":[13,30,79,91,101,121,127,147,153,170,206],"capacitance":[14],"extraction":[15],"of":[16,69,103,112,120,144],"very":[17],"large-scale":[18],"integration":[19],"(VLSI)":[20],"interconnects.":[21],"FRW":[22,70,148],"could":[23],"be":[24],"both":[25,110],"time-consuming":[26],"and":[27,51,84,108,114,126,165,193,201],"power-consuming":[28],"as":[29],"circuit":[31],"scale":[32],"grows.":[33],"However,":[34],"its":[35],"highly":[36],"parallel":[37],"nature":[38],"prompts":[39],"us":[40],"to":[41,55,90,123,141,167,190],"accelerate":[42],"it":[43],"with":[44,156,174],"FPGAs,":[45],"which":[46,161],"have":[47],"shown":[48],"great":[49],"performance":[50,143,192],"energy":[52,195,203],"efficiency":[53,196,204],"potential":[54],"other":[56],"computing":[57],"architectures.":[58],"In":[59],"this":[60],"paper,":[61],"we":[62,150],"propose":[63],"a":[64,198],"scalable":[65],"FPGA/CPU":[66],"heterogeneous":[67],"framework":[68,99],"using":[71],"SDAccel.":[72],"Large-scale":[73],"circuits":[74],"are":[75,87,139],"partitioned":[76],"first":[77],"by":[78,96,116],"CPU":[80],"into":[81],"several":[82],"segments,":[83],"these":[85],"segments":[86],"then":[88],"sent":[89],"FPGA":[92,105,128],"walking":[94,157,175],"one":[95],"one.":[97],"solves":[100],"challenge":[102],"limited":[104],"on-chip":[106],"resource":[107],"integrates":[109],"merits":[111],"FPGAs":[113],"CPUs":[115],"targeting":[117],"separate":[118],"parts":[119],"suitable":[124],"architecture,":[125],"bitstream":[129],"built":[131],"once":[132],"for":[133],"all.":[134],"Several":[135],"kernel":[136],"optimization":[137],"strategies":[138],"maximize":[142],"FPGAs.":[145],"Besides,":[146],"use":[151],"naive":[154],"version":[155,173],"on":[158,176,181,210],"spheres":[159],"(WOS),":[160],"much":[163],"simpler":[164],"easier":[166],"implement":[168],"than":[169],"complicatedly":[171],"optimized":[172],"cubes":[177],"(WOC).":[178],"implementation":[180,209],"AWS":[182],"EC2":[183],"F1":[184],"(Xilinx":[185],"VU9P":[186],"FPGA)":[187],"shows":[188],"up":[189],"6.1x":[191],"42.6x":[194],"over":[197,205],"quad-core":[199],"CPU,":[200],"5.2x":[202],"state-of-the-art":[207],"WOC":[208],"8-core":[212],"CPU.":[213]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
