{"id":"https://openalex.org/W2799178840","doi":"https://doi.org/10.23919/date.2018.8342222","title":"Accelerate analytical placement with GPU: A generic approach","display_name":"Accelerate analytical placement with GPU: A generic approach","publication_year":2018,"publication_date":"2018-03-01","ids":{"openalex":"https://openalex.org/W2799178840","doi":"https://doi.org/10.23919/date.2018.8342222","mag":"2799178840"},"language":"en","primary_location":{"id":"doi:10.23919/date.2018.8342222","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2018.8342222","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084483224","display_name":"Chun-Xun Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chun-Xun Lin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, IL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053378706","display_name":"Martin D. F. Wong","orcid":"https://orcid.org/0000-0001-8274-9688"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Martin D. F. Wong","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, IL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5084483224"],"corresponding_institution_ids":["https://openalex.org/I157725225"],"apc_list":null,"apc_paid":null,"fwci":1.2875,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.80916396,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1345","last_page":"1350"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8288837671279907},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.720206081867218},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.6164344549179077},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.5730947256088257},{"id":"https://openalex.org/keywords/sparse-matrix","display_name":"Sparse matrix","score":0.5557872653007507},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.449920117855072},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3848724067211151},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.35004985332489014},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1270873248577118},{"id":"https://openalex.org/keywords/gaussian","display_name":"Gaussian","score":0.09879744052886963}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8288837671279907},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.720206081867218},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.6164344549179077},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.5730947256088257},{"id":"https://openalex.org/C56372850","wikidata":"https://www.wikidata.org/wiki/Q1050404","display_name":"Sparse matrix","level":3,"score":0.5557872653007507},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.449920117855072},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3848724067211151},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.35004985332489014},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1270873248577118},{"id":"https://openalex.org/C163716315","wikidata":"https://www.wikidata.org/wiki/Q901177","display_name":"Gaussian","level":2,"score":0.09879744052886963},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date.2018.8342222","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2018.8342222","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.550000011920929}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320309480","display_name":"Nvidia","ror":"https://ror.org/03jdj4y14"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1514147299","https://openalex.org/W1976505060","https://openalex.org/W1986026297","https://openalex.org/W1995233983","https://openalex.org/W1996746141","https://openalex.org/W2003145440","https://openalex.org/W2029130826","https://openalex.org/W2041941568","https://openalex.org/W2074140323","https://openalex.org/W2097189804","https://openalex.org/W2108873814","https://openalex.org/W2114871550","https://openalex.org/W2115866417","https://openalex.org/W2117278010","https://openalex.org/W2120985183","https://openalex.org/W2129049238","https://openalex.org/W2161629461","https://openalex.org/W2163190884","https://openalex.org/W2169004268","https://openalex.org/W2479914818","https://openalex.org/W3141126084","https://openalex.org/W4255003042","https://openalex.org/W6644200362"],"related_works":["https://openalex.org/W3213381848","https://openalex.org/W2017587301","https://openalex.org/W2012954338","https://openalex.org/W2005148983","https://openalex.org/W2096672917","https://openalex.org/W2392023973","https://openalex.org/W2939411666","https://openalex.org/W3189307731","https://openalex.org/W2949962288","https://openalex.org/W2364686214"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,78,89,107,122],"generic":[4],"approach":[5,96],"of":[6,25,50,109],"exploiting":[7],"GPU":[8,119,133],"parallelism":[9],"to":[10,53,82,97],"speed":[11],"up":[12],"the":[13,23,47,55,65,71,99,127,131],"essential":[14],"computations":[15],"in":[16,37],"VLSI":[17],"nonlinear":[18,38],"analytical":[19,39],"placement.":[20,40],"We":[21,101],"consider":[22],"computation":[24,79],"wirelength":[26,42],"and":[27,35,69,88,130],"density":[28],"which":[29,62],"are":[30],"widely":[31],"used":[32],"as":[33],"cost":[34],"constraint":[36],"For":[41,74],"gradient":[43],"computing,":[44],"we":[45,76],"utilize":[46],"sparse":[48,59],"characteristic":[49],"circuit":[51],"graph":[52],"transform":[54],"compute-intensive":[56],"portions":[57],"into":[58,94],"matrix":[60],"multiplications,":[61],"effectively":[63],"optimizes":[64],"memory":[66],"access":[67],"pattern":[68],"mitigates":[70],"imbalance":[72],"workload.":[73],"density,":[75],"introduce":[77],"flattening":[80],"technique":[81],"achieve":[83],"load":[84],"balancing":[85],"among":[86],"threads":[87],"High-Precision":[90],"representation":[91],"is":[92],"integrated":[93],"our":[95,104,118],"guarantee":[98],"reproducibility.":[100],"have":[102],"evaluated":[103],"method":[105,120],"on":[106],"set":[108],"contest":[110],"benchmarks":[111],"from":[112],"industry.":[113],"The":[114],"experimental":[115],"results":[116],"demonstrate":[117],"achieves":[121],"better":[123],"performance":[124],"over":[125],"both":[126],"CPU":[128],"methods":[129],"straightforward":[132],"implementation.":[134]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
