{"id":"https://openalex.org/W2775414535","doi":"https://doi.org/10.23919/date.2018.8342171","title":"A time-multiplexed FPGA overlay with linear interconnect","display_name":"A time-multiplexed FPGA overlay with linear interconnect","publication_year":2018,"publication_date":"2018-03-01","ids":{"openalex":"https://openalex.org/W2775414535","doi":"https://doi.org/10.23919/date.2018.8342171","mag":"2775414535"},"language":"en","primary_location":{"id":"doi:10.23919/date.2018.8342171","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2018.8342171","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083911874","display_name":"Xiangwei Li","orcid":"https://orcid.org/0000-0002-1963-6354"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Xiangwei Li","raw_affiliation_strings":["School of Computer Science and Engineering, Nanyang Technological University, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076243389","display_name":"Abhishek Kumar Jain","orcid":"https://orcid.org/0000-0003-3797-029X"},"institutions":[{"id":"https://openalex.org/I1282311441","display_name":"Lawrence Livermore National Laboratory","ror":"https://ror.org/041nk4h53","country_code":"US","type":"facility","lineage":["https://openalex.org/I1282311441","https://openalex.org/I1330989302","https://openalex.org/I198811213","https://openalex.org/I4210138311"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Abhishek Kumar Jain","raw_affiliation_strings":["Lawrence Livermore National Laboratory, United States"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Lawrence Livermore National Laboratory, United States","institution_ids":["https://openalex.org/I1282311441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059218594","display_name":"Douglas L. Maskell","orcid":"https://orcid.org/0000-0002-6588-4762"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Douglas L. Maskell","raw_affiliation_strings":["School of Computer Science and Engineering, Nanyang Technological University, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032556461","display_name":"Suhaib A. Fahmy","orcid":"https://orcid.org/0000-0003-0568-5048"},"institutions":[{"id":"https://openalex.org/I39555362","display_name":"University of Warwick","ror":"https://ror.org/01a77tt86","country_code":"GB","type":"education","lineage":["https://openalex.org/I39555362"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Suhaib A. Fahmy","raw_affiliation_strings":["School of Engineering, University of Warwick, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Engineering, University of Warwick, United Kingdom","institution_ids":["https://openalex.org/I39555362"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1075","last_page":"1080"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7961828112602234},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.759110152721405},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.7564668655395508},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.591407060623169},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5677345991134644},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.49369916319847107},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.47851455211639404},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4350760281085968},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4327211081981659},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.41470324993133545},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3257289528846741},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.25737154483795166},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1867772340774536}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7961828112602234},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.759110152721405},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.7564668655395508},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.591407060623169},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5677345991134644},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.49369916319847107},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.47851455211639404},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4350760281085968},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4327211081981659},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.41470324993133545},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3257289528846741},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.25737154483795166},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1867772340774536},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.23919/date.2018.8342171","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2018.8342171","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},{"id":"pmh:oai:wrap.warwick.ac.uk:95603","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4306400665","display_name":"Warwick Research Archive Portal (University of Warwick)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I39555362","host_organization_name":"University of Warwick","host_organization_lineage":["https://openalex.org/I39555362"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"Conference Item"},{"id":"pmh:oai:wrap.warwick.ac.uk:121845","is_oa":false,"landing_page_url":"http://wrap.warwick.ac.uk/121845/","pdf_url":null,"source":{"id":"https://openalex.org/S4306400665","display_name":"Warwick Research Archive Portal (University of Warwick)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I39555362","host_organization_name":"University of Warwick","host_organization_lineage":["https://openalex.org/I39555362"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference Item"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth","score":0.47999998927116394}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W105298322","https://openalex.org/W1644436786","https://openalex.org/W1970047515","https://openalex.org/W1986687470","https://openalex.org/W1998922872","https://openalex.org/W2012512596","https://openalex.org/W2022497217","https://openalex.org/W2037748535","https://openalex.org/W2081889466","https://openalex.org/W2096081777","https://openalex.org/W2107350738","https://openalex.org/W2113263062","https://openalex.org/W2122942724","https://openalex.org/W2123412205","https://openalex.org/W2141418654","https://openalex.org/W2147961213","https://openalex.org/W2187912924","https://openalex.org/W2279391168","https://openalex.org/W2411785910","https://openalex.org/W2418145342","https://openalex.org/W2473737183","https://openalex.org/W2554510265","https://openalex.org/W2620282837","https://openalex.org/W4241238426","https://openalex.org/W4241765343","https://openalex.org/W4249499534","https://openalex.org/W6646810721","https://openalex.org/W6721028420"],"related_works":["https://openalex.org/W595346907","https://openalex.org/W153296825","https://openalex.org/W598989511","https://openalex.org/W2375779923","https://openalex.org/W1967800214","https://openalex.org/W2055675609","https://openalex.org/W2245277136","https://openalex.org/W3013668398","https://openalex.org/W2258948885","https://openalex.org/W1998753618"],"abstract_inverted_index":{"Coarse-grained":[0],"overlays":[1,17,34,44,96],"improve":[2,175],"FPGA":[3,37,71,100,147,157],"design":[4],"productivity":[5],"by":[6,60],"providing":[7],"fast":[8],"compilation":[9],"and":[10,84,109,144,155,179,195],"software":[11],"like":[12],"programmability.":[13],"Soft":[14],"processor":[15],"based":[16,127,171],"with":[18,130,190],"well-defined":[19],"ISAs":[20],"are":[21,51,107],"attractive":[22],"to":[23,27,53,151,167,174],"application":[24,105,141],"developers":[25],"due":[26],"their":[28,55],"ease":[29],"of":[30,78,93,139,164],"use.":[31],"However,":[32,103],"these":[33],"have":[35],"significant":[36],"resource":[38,72,101,158],"overheads.":[39],"Time":[40],"multiplexed":[41],"(TM)":[42],"CGRA-like":[43,95],"represent":[45],"an":[46,184],"interesting":[47],"alternative":[48],"as":[49,150],"they":[50],"able":[52],"change":[54],"behavior":[56],"on":[57],"a":[58,79,114,124,162],"cycle":[59,61],"basis":[62],"while":[63],"the":[64,70,76,134,140,145,153,156,168,176],"compute":[65],"kernel":[66],"executes.":[67],"This":[68,121],"reduces":[69],"needed,":[73],"but":[74],"at":[75],"cost":[77],"higher":[80],"initiation":[81],"interval":[82],"(II)":[83],"hence":[85],"reduced":[86],"throughput.":[87],"The":[88,181],"fully":[89],"flexible":[90],"routing":[91,119],"network":[92],"current":[94],"results":[97,182],"in":[98,188,193],"high":[99],"usage.":[102,159],"many":[104],"kernels":[106],"acyclic":[108],"can":[110],"be":[111],"implemented":[112],"using":[113],"much":[115],"simpler":[116],"linear":[117,131],"feed-forward":[118],"network.":[120],"paper":[122],"examines":[123],"DSP":[125,169],"block":[126,170],"TM":[128],"overlay":[129,135],"interconnect":[132],"where":[133],"architecture":[136],"takes":[137],"account":[138],"kernels'":[142],"characteristics":[143],"underlying":[146],"architecture,":[148],"so":[149],"minimize":[152],"II":[154],"We":[160],"examine":[161],"number":[163],"architectural":[165],"extensions":[166],"functional":[172],"unit":[173],"II,":[177,189],"throughput":[178,194],"latency.":[180,196],"show":[183],"average":[185],"70%":[186],"reduction":[187],"corresponding":[191],"improvements":[192]},"counts_by_year":[{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
