{"id":"https://openalex.org/W2798329677","doi":"https://doi.org/10.23919/date.2018.8342155","title":"An industrial case study of low cost adaptive voltage scaling using delay test patterns","display_name":"An industrial case study of low cost adaptive voltage scaling using delay test patterns","publication_year":2018,"publication_date":"2018-03-01","ids":{"openalex":"https://openalex.org/W2798329677","doi":"https://doi.org/10.23919/date.2018.8342155","mag":"2798329677"},"language":"en","primary_location":{"id":"doi:10.23919/date.2018.8342155","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2018.8342155","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012265083","display_name":"Mahroo Zandrahimi","orcid":"https://orcid.org/0000-0003-2496-6320"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Mahroo Zandrahimi","raw_affiliation_strings":["Delft University of Technology, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Delft University of Technology, The Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084340774","display_name":"Philippe Debaud","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Philippe Debaud","raw_affiliation_strings":["STMicroelectronics, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049770924","display_name":"Armand Castillejo","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Armand Castillejo","raw_affiliation_strings":["STMicroelectronics, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021955713","display_name":"Zaid Al-Ars","orcid":"https://orcid.org/0000-0001-7670-8572"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Zaid Al-Ars","raw_affiliation_strings":["Delft University of Technology, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Delft University of Technology, The Netherlands","institution_ids":["https://openalex.org/I98358874"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5012265083"],"corresponding_institution_ids":["https://openalex.org/I98358874"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.04399902,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"999","last_page":"1000"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6609755158424377},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5889976024627686},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5631471276283264},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.5534734725952148},{"id":"https://openalex.org/keywords/silicon-on-insulator","display_name":"Silicon on insulator","score":0.5476759672164917},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5263479948043823},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.5141292214393616},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.5087774395942688},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.48892298340797424},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.48171931505203247},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.42963874340057373},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.42841625213623047},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.417593389749527},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4033295214176178},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2633005380630493},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21724233031272888},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14269477128982544},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.12786388397216797},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.12188953161239624},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08120682835578918}],"concepts":[{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6609755158424377},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5889976024627686},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5631471276283264},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.5534734725952148},{"id":"https://openalex.org/C53143962","wikidata":"https://www.wikidata.org/wiki/Q1478788","display_name":"Silicon on insulator","level":3,"score":0.5476759672164917},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5263479948043823},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.5141292214393616},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.5087774395942688},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.48892298340797424},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.48171931505203247},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.42963874340057373},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.42841625213623047},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.417593389749527},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4033295214176178},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2633005380630493},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21724233031272888},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14269477128982544},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.12786388397216797},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.12188953161239624},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08120682835578918},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date.2018.8342155","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2018.8342155","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2036326004","https://openalex.org/W2114883494","https://openalex.org/W2143165581","https://openalex.org/W2167729301","https://openalex.org/W6684363790"],"related_works":["https://openalex.org/W2141405780","https://openalex.org/W4382130817","https://openalex.org/W2104315811","https://openalex.org/W2142217172","https://openalex.org/W2146978563","https://openalex.org/W1982273910","https://openalex.org/W1929041301","https://openalex.org/W4230312832","https://openalex.org/W2110366946","https://openalex.org/W2170610805"],"abstract_inverted_index":{"In":[0],"deep":[1],"sub-micron":[2],"technologies,":[3],"the":[4,40,86,92,105,133],"increasing":[5,33],"effect":[6,34],"of":[7,35,42,97],"process":[8,36],"and":[9,59,90],"environmental":[10],"variations":[11],"has":[12],"lead":[13],"chip":[14,44],"manufacturers":[15],"to":[16,24,29,84,100,136],"use":[17],"adaptive":[18,74],"voltage":[19,75],"scaling":[20,76],"techniques":[21],"in":[22,56],"order":[23],"adapt":[25],"operation":[26],"parameters":[27],"exclusively":[28],"each":[30,101],"chip.":[31],"The":[32],"variation":[37],"is":[38,82],"limiting":[39],"effectiveness":[41],"current":[43],"monitoring":[45],"approaches,":[46],"such":[47],"as":[48,107,109],"on-chip":[49],"performance":[50,130],"monitor":[51],"boxes":[52],"(PMBs),":[53],"which":[54,81],"results":[55],"yield":[57,106],"loss":[58],"high":[60,64],"design":[61],"margins,":[62],"thus":[63,91],"power":[65,110,124],"consumption.":[66],"This":[67],"paper":[68],"proposes":[69],"an":[70,115],"alternative":[71],"solution":[72],"for":[73,88,122,129],"using":[77,114],"delay":[78,127],"test":[79],"patterns,":[80],"able":[83],"eliminate":[85],"need":[87],"PMBs,":[89],"long":[93],"expensive":[94],"characterization":[95],"phase":[96],"tuning":[98],"PMBs":[99],"design,":[102],"while":[103],"improving":[104],"well":[108],"optimization.":[111],"Results":[112],"show,":[113],"industrial":[116],"grade":[117],"28nm":[118],"FD-SOI":[119],"library":[120],"developed":[121],"low":[123],"devices,":[125],"that":[126],"testing":[128],"prediction":[131],"reduces":[132],"inaccuracy":[134],"down":[135],"1.85%.":[137]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
