{"id":"https://openalex.org/W2799027281","doi":"https://doi.org/10.23919/date.2018.8342110","title":"Technology mapping flow for emerging reconfigurable silicon nanowire transistors","display_name":"Technology mapping flow for emerging reconfigurable silicon nanowire transistors","publication_year":2018,"publication_date":"2018-03-01","ids":{"openalex":"https://openalex.org/W2799027281","doi":"https://doi.org/10.23919/date.2018.8342110","mag":"2799027281"},"language":"en","primary_location":{"id":"doi:10.23919/date.2018.8342110","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2018.8342110","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075349265","display_name":"Shubham Rai","orcid":"https://orcid.org/0000-0002-6522-5628"},"institutions":[{"id":"https://openalex.org/I4405266956","display_name":"Center for Advancing Electronics Dresden","ror":"https://ror.org/00g3vrr12","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4405266956","https://openalex.org/I78650965"]},{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Shubham Rai","raw_affiliation_strings":["Chair For Processor Design, CfAED, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair For Processor Design, CfAED, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I4405266956","https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060193481","display_name":"Michael Raitza","orcid":"https://orcid.org/0000-0003-2370-4054"},"institutions":[{"id":"https://openalex.org/I4405266956","display_name":"Center for Advancing Electronics Dresden","ror":"https://ror.org/00g3vrr12","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4405266956","https://openalex.org/I78650965"]},{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Michael Raitza","raw_affiliation_strings":["Chair For Processor Design, CfAED, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair For Processor Design, CfAED, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I4405266956","https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100755285","display_name":"Akash Kumar","orcid":"https://orcid.org/0000-0001-7125-1737"},"institutions":[{"id":"https://openalex.org/I4405266956","display_name":"Center for Advancing Electronics Dresden","ror":"https://ror.org/00g3vrr12","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4405266956","https://openalex.org/I78650965"]},{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Akash Kumar","raw_affiliation_strings":["Chair For Processor Design, CfAED, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair For Processor Design, CfAED, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I4405266956","https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"767","last_page":"772"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11272","display_name":"Nanowire Synthesis and Applications","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.8751773834228516},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6426951289176941},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6049243807792664},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5671162009239197},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5407268404960632},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5191073417663574},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5061168074607849},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4769905209541321},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.45837923884391785},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4503723680973053},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.4357275366783142},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4092002809047699},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3601435124874115},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.2749835252761841},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26262032985687256},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2145404815673828},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.10427466034889221},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08965739607810974}],"concepts":[{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.8751773834228516},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6426951289176941},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6049243807792664},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5671162009239197},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5407268404960632},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5191073417663574},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5061168074607849},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4769905209541321},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.45837923884391785},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4503723680973053},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.4357275366783142},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4092002809047699},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3601435124874115},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.2749835252761841},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26262032985687256},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2145404815673828},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10427466034889221},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08965739607810974},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date.2018.8342110","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2018.8342110","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.49000000953674316,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1508262445","https://openalex.org/W1528837436","https://openalex.org/W1776822698","https://openalex.org/W1879281873","https://openalex.org/W1984163270","https://openalex.org/W1995135231","https://openalex.org/W2011829553","https://openalex.org/W2036887642","https://openalex.org/W2045823846","https://openalex.org/W2055215434","https://openalex.org/W2165952540","https://openalex.org/W2322754293","https://openalex.org/W2346682451","https://openalex.org/W2574807302","https://openalex.org/W2587608034","https://openalex.org/W2587804194","https://openalex.org/W6649101775","https://openalex.org/W6653525883"],"related_works":["https://openalex.org/W1922599229","https://openalex.org/W4385309418","https://openalex.org/W1966764473","https://openalex.org/W2082788688","https://openalex.org/W1488117239","https://openalex.org/W3147061323","https://openalex.org/W3128899411","https://openalex.org/W2227166741","https://openalex.org/W2104308620","https://openalex.org/W2130825721"],"abstract_inverted_index":{"Efficient":[0],"circuit":[1,16,57],"designs":[2],"can":[3],"make":[4],"use":[5,20,64],"of":[6,9,78,85,90,95,110,120,176],"ambipolar":[7,178],"nature":[8],"silicon":[10],"nanowire":[11],"(SiNW)":[12],"over":[13],"CMOS.":[14],"Conventional":[15],"Design-Flow":[17],"fails":[18],"to":[19,69,82,124,169],"this":[21,48,61,71],"inherent":[22],"functional":[23],"flexibility":[24],"as":[25,122],"CMOS":[26,125],"based":[27,112,145,155],"mapping":[28,45,106],"considers":[29],"a":[30],"single":[31],"logical":[32],"output":[33],"from":[34],"logic":[35,99,113,146],"gates.":[36,147],"To":[37,59],"address":[38],"this,":[39],"we":[40,63,133],"propose":[41],"an":[42,118],"area-optimized":[43],"technology":[44,105],"which":[46],"uses":[47],"innate":[49],"reconfigurability,":[50],"offered":[51],"by":[52,117],"SiNW":[53,79,111,144,154],"transistors":[54],"for":[55,92,97,127,137,143,173],"efficient":[56],"designs.":[58],"enable":[60,170],"objective,":[62],"higher":[65],"order":[66],"functions":[67],"(HOF)":[68],"encapsulate":[70],"extended":[72],"functionality.":[73],"Additionally,":[74],"the":[75,86,152,158],"electrical":[76],"properties":[77],"allow":[80],"us":[81],"take":[83],"advantage":[84],"available":[87,164],"inverted":[88],"forms":[89],"fan-ins":[91],"additional":[93],"savings":[94],"area":[96,109],"XOR":[98],"family.":[100],"Experimental":[101],"results":[102],"using":[103],"our":[104,135],"show":[107],"that":[108],"design":[114],"is":[115,162],"less":[116],"average":[119],"18.38%":[121],"compared":[123],"flow":[126,136,150],"complete":[128],"MCNC":[129],"benchmarks":[130],"suite.":[131],"Further,":[132],"evaluate":[134],"both":[138],"reconfigurability-aware":[139],"and":[140,157],"static":[141],"layout":[142],"The":[148],"whole":[149],"including":[151],"new":[153],"genlib":[156],"modified":[159],"ABC":[160],"tool":[161],"made":[163],"under":[165],"open":[166],"source":[167],"license":[168],"further":[171],"research":[172],"any":[174],"kind":[175],"emerging":[177],"transistors.":[179]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":7},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}