{"id":"https://openalex.org/W2798487558","doi":"https://doi.org/10.23919/date.2018.8342109","title":"Logic optimization with considering boolean relations","display_name":"Logic optimization with considering boolean relations","publication_year":2018,"publication_date":"2018-03-01","ids":{"openalex":"https://openalex.org/W2798487558","doi":"https://doi.org/10.23919/date.2018.8342109","mag":"2798487558"},"language":"en","primary_location":{"id":"doi:10.23919/date.2018.8342109","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2018.8342109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084910775","display_name":"Tung-Yuan Lee","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Tung-Yuan Lee","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsincu, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsincu, Taiwan, R.O.C","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014356744","display_name":"Chia\u2010Cheng Wu","orcid":"https://orcid.org/0000-0001-9870-8290"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chia-Cheng Wu","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsincu, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsincu, Taiwan, R.O.C","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058932938","display_name":"Chia-Chun Lin","orcid":"https://orcid.org/0000-0002-0136-9825"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chia-Chun Lin","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsincu, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsincu, Taiwan, R.O.C","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101882689","display_name":"Yung\u2010Chih Chen","orcid":"https://orcid.org/0000-0002-3934-800X"},"institutions":[{"id":"https://openalex.org/I99908691","display_name":"Yuan Ze University","ror":"https://ror.org/01fv1ds98","country_code":"TW","type":"education","lineage":["https://openalex.org/I99908691"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yung-Chih Chen","raw_affiliation_strings":["Department of Computer Science and Engineering, Yuan Ze University, Chungli, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Yuan Ze University, Chungli, Taiwan, R.O.C","institution_ids":["https://openalex.org/I99908691"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5115602054","display_name":"Chun-Yao Wang","orcid":"https://orcid.org/0000-0002-4536-214X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chun-Yao Wang","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsincu, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsincu, Taiwan, R.O.C","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5084910775"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.04461012,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"761","last_page":"766"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.7605335712432861},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6835187077522278},{"id":"https://openalex.org/keywords/boolean-circuit","display_name":"Boolean circuit","score":0.6275686025619507},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.6030144095420837},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6027089357376099},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6003506183624268},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5074257254600525},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5044652223587036},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.5014615058898926},{"id":"https://openalex.org/keywords/relation","display_name":"Relation (database)","score":0.48664340376853943},{"id":"https://openalex.org/keywords/circuit-minimization-for-boolean-functions","display_name":"Circuit minimization for Boolean functions","score":0.46762165427207947},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4426802694797516},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.4304830729961395},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4279324412345886},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4258122742176056},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41909900307655334},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20637857913970947},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.16044580936431885},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08363568782806396},{"id":"https://openalex.org/keywords/data-mining","display_name":"Data mining","score":0.08151772618293762}],"concepts":[{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.7605335712432861},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6835187077522278},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.6275686025619507},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.6030144095420837},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6027089357376099},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6003506183624268},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5074257254600525},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5044652223587036},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.5014615058898926},{"id":"https://openalex.org/C25343380","wikidata":"https://www.wikidata.org/wiki/Q277521","display_name":"Relation (database)","level":2,"score":0.48664340376853943},{"id":"https://openalex.org/C94992772","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Circuit minimization for Boolean functions","level":4,"score":0.46762165427207947},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4426802694797516},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.4304830729961395},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4279324412345886},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4258122742176056},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41909900307655334},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20637857913970947},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.16044580936431885},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08363568782806396},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.08151772618293762},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date.2018.8342109","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2018.8342109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1518386595","https://openalex.org/W1971654502","https://openalex.org/W2003958683","https://openalex.org/W2011342051","https://openalex.org/W2018094844","https://openalex.org/W2040464422","https://openalex.org/W2121772494","https://openalex.org/W2127330146","https://openalex.org/W2139223470","https://openalex.org/W2153827989","https://openalex.org/W2154291650","https://openalex.org/W2157591717","https://openalex.org/W2165727602","https://openalex.org/W2167472794","https://openalex.org/W2335478831","https://openalex.org/W2787265165","https://openalex.org/W3150965154","https://openalex.org/W3178812393","https://openalex.org/W4253456425","https://openalex.org/W4254127407","https://openalex.org/W4285719527","https://openalex.org/W6677551757","https://openalex.org/W6682779062","https://openalex.org/W6684714198"],"related_works":["https://openalex.org/W2157200699","https://openalex.org/W1552215787","https://openalex.org/W2066518505","https://openalex.org/W3144289157","https://openalex.org/W2798487558","https://openalex.org/W3140504325","https://openalex.org/W2039439542","https://openalex.org/W2112458228","https://openalex.org/W1995425391","https://openalex.org/W2483997392"],"abstract_inverted_index":{"Boolean":[0],"Relation":[1],"(BR)":[2],"is":[3],"a":[4,32,41,69],"many-to-many":[5],"mapping":[6],"between":[7],"two":[8],"domains.":[9],"Logic":[10],"optimization":[11,34],"considering":[12,36],"BR":[13,53],"can":[14,95,112],"exploit":[15],"the":[16,25,51,55,59,63,89,107],"potential":[17],"flexibility":[18],"existed":[19],"in":[20,54,82,116],"logic":[21,33],"networks":[22],"to":[23],"minimize":[24],"circuits.":[26],"In":[27],"this":[28],"paper,":[29],"we":[30,101,111],"present":[31],"approach":[35,39,104],"BR.":[37],"The":[38,84],"identifies":[40],"proper":[42],"sub-circuit":[43,56],"and":[44],"locally":[45],"changes":[46],"its":[47],"functionality":[48,61],"by":[49,79,106],"solving":[50],"corresponding":[52],"without":[57],"altering":[58],"overall":[60],"of":[62,71,92],"circuit.":[64],"We":[65],"conducted":[66],"experiments":[67],"on":[68],"set":[70],"MCNC":[72],"benchmarks":[73,94],"that":[74,88],"cannot":[75],"be":[76,96],"further":[77,97],"optimized":[78],"resyn2":[80,108],"script":[81,109],"ABC.":[83],"experimental":[85],"results":[86],"show":[87],"node":[90],"counts":[91],"these":[93],"reduced.":[98],"Additionally,":[99],"when":[100],"apply":[102],"our":[103],"followed":[105],"repeatedly,":[110],"obtain":[113],"6.11%":[114],"improvements":[115],"average.":[117]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
