{"id":"https://openalex.org/W2612066875","doi":"https://doi.org/10.23919/date.2017.7927229","title":"Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation","display_name":"Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation","publication_year":2017,"publication_date":"2017-03-01","ids":{"openalex":"https://openalex.org/W2612066875","doi":"https://doi.org/10.23919/date.2017.7927229","mag":"2612066875"},"language":"en","primary_location":{"id":"doi:10.23919/date.2017.7927229","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927229","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002187268","display_name":"Taesik Na","orcid":"https://orcid.org/0000-0003-2039-3772"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Taesik Na","raw_affiliation_strings":["School of ECE, Georgia Institute of Technology, Atlanta, Georgia, USA"],"affiliations":[{"raw_affiliation_string":"School of ECE, Georgia Institute of Technology, Atlanta, Georgia, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063908850","display_name":"Jong Hwan Ko","orcid":"https://orcid.org/0000-0003-4434-4318"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jong Hwan Ko","raw_affiliation_strings":["School of ECE, Georgia Institute of Technology, Atlanta, Georgia, USA"],"affiliations":[{"raw_affiliation_string":"School of ECE, Georgia Institute of Technology, Atlanta, Georgia, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009591041","display_name":"Saibal Mukhopadhyay","orcid":"https://orcid.org/0000-0002-8894-3390"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saibal Mukhopadhyay","raw_affiliation_strings":["School of ECE, Georgia Institute of Technology, Atlanta, Georgia, USA"],"affiliations":[{"raw_affiliation_string":"School of ECE, Georgia Institute of Technology, Atlanta, Georgia, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5002187268"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":0.1433,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.48400709,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1504","last_page":"1509"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.7600662708282471},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7341327667236328},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.677412748336792},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6661267280578613},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.6174878478050232},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6088373064994812},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.5517892837524414},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.5000796318054199},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49398547410964966},{"id":"https://openalex.org/keywords/clock-drift","display_name":"Clock drift","score":0.47896721959114075},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4486961364746094},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4363189935684204},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.27227166295051575},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.18352004885673523},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17723369598388672},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09699833393096924}],"concepts":[{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.7600662708282471},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7341327667236328},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.677412748336792},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6661267280578613},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.6174878478050232},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6088373064994812},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.5517892837524414},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.5000796318054199},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49398547410964966},{"id":"https://openalex.org/C155837451","wikidata":"https://www.wikidata.org/wiki/Q1069144","display_name":"Clock drift","level":5,"score":0.47896721959114075},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4486961364746094},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4363189935684204},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27227166295051575},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.18352004885673523},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17723369598388672},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09699833393096924}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date.2017.7927229","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927229","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8399999737739563}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320332162","display_name":"Centers for Disease Control and Prevention","ror":"https://ror.org/042twtr12"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2035713928","https://openalex.org/W2051192488","https://openalex.org/W2063924131","https://openalex.org/W2178304595","https://openalex.org/W2345718979","https://openalex.org/W2497661072","https://openalex.org/W2788706082"],"related_works":["https://openalex.org/W2169618112","https://openalex.org/W3006003651","https://openalex.org/W2224788396","https://openalex.org/W2205497670","https://openalex.org/W2125201667","https://openalex.org/W4313332229","https://openalex.org/W4231008241","https://openalex.org/W2286776167","https://openalex.org/W2386103431","https://openalex.org/W2139338465"],"abstract_inverted_index":{"Adaptive":[0],"clock":[1,25,34,56,74,85,110,126],"generation":[2],"to":[3,23,30,115],"track":[4],"critical":[5,69,88],"path":[6,70,89],"delay":[7,81],"enables":[8],"lowering":[9],"supply":[10,17,100],"voltage":[11],"with":[12,124],"improved":[13],"timing":[14,96,117],"slack":[15,97,118],"under":[16,98,119],"noise.":[18],"This":[19],"paper":[20,43,60,78,105],"presents":[21],"how":[22],"synthesize":[24],"tree":[26,75,86,111],"in":[27,39,65,121],"adaptive":[28,125],"clocking":[29],"fully":[31],"exploit":[32],"the":[33,59,80,104],"data":[35],"compensation":[36],"(CDC)":[37],"effect":[38,51,64,93],"digital":[40,122],"circuits.":[41],"The":[42,77],"first":[44],"provides":[45],"analytical":[46],"proof":[47],"of":[48],"ideal":[49],"CDC":[50,63,92],"for":[52],"ring":[53],"oscillator":[54],"based":[55],"generation.":[57,127],"Second,":[58],"analyzes":[61],"non-ideal":[62],"a":[66],"gate":[67],"dominated":[68,73],"and":[71,87],"wire":[72],"design.":[76],"shows":[79],"sensitivity":[82],"mismatch":[83],"between":[84],"can":[90],"degrade":[91],"by":[94],"analyzing":[95],"power":[99],"noise":[101],"(PSN).":[102],"Finally,":[103],"proposes":[106],"simple":[107],"but":[108],"efficient":[109],"synthesis":[112],"(CTS)":[113],"technique":[114],"maximize":[116],"PSN":[120],"circuits":[123]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}