{"id":"https://openalex.org/W2612536903","doi":"https://doi.org/10.23919/date.2017.7927194","title":"Logic optimization and synthesis: Trends and directions in industry","display_name":"Logic optimization and synthesis: Trends and directions in industry","publication_year":2017,"publication_date":"2017-03-01","ids":{"openalex":"https://openalex.org/W2612536903","doi":"https://doi.org/10.23919/date.2017.7927194","mag":"2612536903"},"language":"en","primary_location":{"id":"doi:10.23919/date.2017.7927194","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927194","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023405941","display_name":"Luca Amar\u00f9","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Luca Amaru","raw_affiliation_strings":["Synopsys Inc., Design Group, Sunnyvale, California, USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Design Group, Sunnyvale, California, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006756374","display_name":"Patrick Vuillod","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Patrick Vuillod","raw_affiliation_strings":["Synopsys Inc., Design Group, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Design Group, Grenoble, France","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015217224","display_name":"Jiong Luo","orcid":"https://orcid.org/0009-0006-2158-5804"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiong Luo","raw_affiliation_strings":["Synopsys Inc., Design Group, Sunnyvale, California, USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Design Group, Sunnyvale, California, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056936470","display_name":"Janet Olson","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Janet Olson","raw_affiliation_strings":["Synopsys Inc., Design Group, Sunnyvale, California, USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Design Group, Sunnyvale, California, USA","institution_ids":["https://openalex.org/I4210088951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5023405941"],"corresponding_institution_ids":["https://openalex.org/I4210088951"],"apc_list":null,"apc_paid":null,"fwci":0.8601,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.75132794,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1303","last_page":"1305"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6524933576583862},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6346149444580078},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.529079020023346},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4942188560962677},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4864520728588104},{"id":"https://openalex.org/keywords/electronics","display_name":"Electronics","score":0.47875919938087463},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46605974435806274},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4624135494232178},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3258313834667206},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2151872217655182},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20663335919380188},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1792474091053009},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1343366801738739}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6524933576583862},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6346149444580078},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.529079020023346},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4942188560962677},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4864520728588104},{"id":"https://openalex.org/C138331895","wikidata":"https://www.wikidata.org/wiki/Q11650","display_name":"Electronics","level":2,"score":0.47875919938087463},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46605974435806274},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4624135494232178},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3258313834667206},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2151872217655182},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20663335919380188},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1792474091053009},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1343366801738739},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date.2017.7927194","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927194","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6600000262260437,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1918485682","https://openalex.org/W2018094844","https://openalex.org/W2055215434","https://openalex.org/W2100465945","https://openalex.org/W2105925860","https://openalex.org/W2118182815","https://openalex.org/W2121290756","https://openalex.org/W2293875967","https://openalex.org/W4248136059"],"related_works":["https://openalex.org/W1966764473","https://openalex.org/W2098419840","https://openalex.org/W2614722573","https://openalex.org/W3147061323","https://openalex.org/W2121963733","https://openalex.org/W2789349722","https://openalex.org/W2118796996","https://openalex.org/W1977171228","https://openalex.org/W2102927888","https://openalex.org/W4249951793"],"abstract_inverted_index":{"Logic":[0],"synthesis":[1,27,54,68,79,103,115,132],"is":[2],"a":[3,145],"key":[4],"design":[5,58],"step":[6],"which":[7,81],"optimizes":[8],"abstract":[9],"circuit":[10],"representations":[11],"and":[12,69,98,104],"links":[13],"them":[14],"to":[15,29,55],"technology.":[16],"With":[17,39],"CMOS":[18],"technology":[19,48,149],"moving":[20],"into":[21],"the":[22,37,40,50,64,87,110,118,137],"deep":[23],"nanometer":[24],"regime,":[25],"logic":[26,53,67],"needs":[28,49],"be":[30],"aware":[31],"of":[32,42,52,95,112,121,139,148],"physical":[33,84,105],"informations":[34,85],"early":[35,119],"in":[36,117],"flow.":[38],"rise":[41],"enhanced":[43,125],"functionality":[44],"nanodevices,":[45],"research":[46],"on":[47],"help":[51],"capture":[56],"advantageous":[57],"opportunities.":[59],"This":[60],"paper":[61],"deals":[62],"with":[63,124],"synergy":[65],"between":[66,101],"technology,":[70],"from":[71],"an":[72],"industrial":[73],"perspective.":[74],"First,":[75],"we":[76,108,128,142],"present":[77],"new":[78,114,131],"techniques":[80,116],"embed":[82],"detailed":[83],"at":[86],"core":[88],"optimization":[89],"engine.":[90],"Experiments":[91],"show":[92],"improved":[93],"Quality":[94],"Results":[96],"(QoR)":[97],"better":[99],"correlation":[100],"RTL":[102],"implementation.":[106],"Second,":[107],"discuss":[109],"application":[111],"these":[113],"assessment":[120],"emerging":[122],"nanodevices":[123],"functionality.":[126],"Finally,":[127],"argue":[129],"that":[130],"methods":[133],"can":[134],"push":[135],"further":[136],"progress":[138],"electronics,":[140],"as":[141],"have":[143],"reached":[144],"multiforking":[146],"point":[147],"where":[150],"choices":[151],"are":[152],"tougher":[153],"than":[154],"ever.":[155]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}