{"id":"https://openalex.org/W2592304361","doi":"https://doi.org/10.23919/date.2017.7927152","title":"Endurance management for resistive Logic-In-Memory computing architectures","display_name":"Endurance management for resistive Logic-In-Memory computing architectures","publication_year":2017,"publication_date":"2017-03-01","ids":{"openalex":"https://openalex.org/W2592304361","doi":"https://doi.org/10.23919/date.2017.7927152","mag":"2592304361"},"language":"en","primary_location":{"id":"doi:10.23919/date.2017.7927152","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2017","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/224351","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069467241","display_name":"Saeideh Shirinzadeh","orcid":"https://orcid.org/0000-0002-8824-1428"},"institutions":[{"id":"https://openalex.org/I180437899","display_name":"University of Bremen","ror":"https://ror.org/04ers2y35","country_code":"DE","type":"education","lineage":["https://openalex.org/I180437899"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Saeideh Shirinzadeh","raw_affiliation_strings":["Department of Mathematics and Computer Science, University of Bremen, Germany"],"affiliations":[{"raw_affiliation_string":"Department of Mathematics and Computer Science, University of Bremen, Germany","institution_ids":["https://openalex.org/I180437899"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084007478","display_name":"Mathias Soeken","orcid":"https://orcid.org/0000-0002-0229-8766"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Mathias Soeken","raw_affiliation_strings":["Integrated Systems Laboratory, EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002568331","display_name":"Pierre\u2010Emmanuel Gaillardon","orcid":"https://orcid.org/0000-0003-3634-3999"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pierre-Emmanuel Gaillardon","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Utah, Salt Lake City, UT, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Utah, Salt Lake City, UT, USA","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["Integrated Systems Laboratory, EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071742136","display_name":"Rolf Drechsler","orcid":"https://orcid.org/0000-0002-9872-1740"},"institutions":[{"id":"https://openalex.org/I33256026","display_name":"German Research Centre for Artificial Intelligence","ror":"https://ror.org/01ayc5b57","country_code":"DE","type":"funder","lineage":["https://openalex.org/I33256026"]},{"id":"https://openalex.org/I180437899","display_name":"University of Bremen","ror":"https://ror.org/04ers2y35","country_code":"DE","type":"education","lineage":["https://openalex.org/I180437899"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rolf Drechsler","raw_affiliation_strings":["Cyber-Physical Systems, DFKI GmbH, Bremen, Germany","Department of Mathematics and Computer Science, University of Bremen, Germany"],"affiliations":[{"raw_affiliation_string":"Cyber-Physical Systems, DFKI GmbH, Bremen, Germany","institution_ids":["https://openalex.org/I33256026"]},{"raw_affiliation_string":"Department of Mathematics and Computer Science, University of Bremen, Germany","institution_ids":["https://openalex.org/I180437899"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5069467241"],"corresponding_institution_ids":["https://openalex.org/I180437899"],"apc_list":null,"apc_paid":null,"fwci":1.4602,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.82913223,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.8267985582351685},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7844732403755188},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5849071145057678},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.4541867971420288},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4312681555747986},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3742215037345886},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37326520681381226},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35389187932014465},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34692150354385376},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1972571611404419},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10047587752342224},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0901578962802887}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.8267985582351685},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7844732403755188},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5849071145057678},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.4541867971420288},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4312681555747986},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3742215037345886},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37326520681381226},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35389187932014465},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34692150354385376},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1972571611404419},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10047587752342224},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0901578962802887},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.23919/date.2017.7927152","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2017","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.epfl.ch:224351","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/224351","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:224351","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/224351","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[{"score":0.4300000071525574,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1549725729","https://openalex.org/W1776822698","https://openalex.org/W2004640050","https://openalex.org/W2006798699","https://openalex.org/W2025674646","https://openalex.org/W2036687738","https://openalex.org/W2066280488","https://openalex.org/W2076739924","https://openalex.org/W2081729575","https://openalex.org/W2084379018","https://openalex.org/W2112753327","https://openalex.org/W2112768159","https://openalex.org/W2122148191","https://openalex.org/W2125263803","https://openalex.org/W2130657217","https://openalex.org/W2135393827","https://openalex.org/W2140975144","https://openalex.org/W2165310699","https://openalex.org/W2268392721","https://openalex.org/W2286699138","https://openalex.org/W2315794112","https://openalex.org/W2345622364","https://openalex.org/W6632791987","https://openalex.org/W6704402733"],"related_works":["https://openalex.org/W2076211355","https://openalex.org/W2533127403","https://openalex.org/W2007070351","https://openalex.org/W2033811947","https://openalex.org/W2183989414","https://openalex.org/W1551399929","https://openalex.org/W2410132916","https://openalex.org/W989761102","https://openalex.org/W2162174949","https://openalex.org/W2104937488"],"abstract_inverted_index":{"Resistive":[0],"Random":[1],"Access":[2],"Memory":[3],"(RRAM)":[4],"is":[5,85],"a":[6,33,48,59,68,105,131],"promising":[7],"non-volatile":[8],"memory":[9,44],"technology":[10],"which":[11],"enables":[12],"modern":[13],"in-memory":[14],"computing":[15],"architectures.":[16,57],"Although":[17],"RRAMs":[18],"are":[19],"known":[20],"to":[21,24,50,130],"be":[22,123],"superior":[23],"conventional":[25],"memories":[26],"in":[27,67],"many":[28],"aspects,":[29],"they":[30],"suffer":[31],"from":[32],"low":[34],"write":[35,45,65,92],"endurance.":[36],"In":[37],"this":[38],"paper,":[39],"we":[40,62],"focus":[41],"on":[42,104,127],"balancing":[43],"traffic":[46,66],"as":[47],"solution":[49],"extend":[51],"the":[52,64,98,117,135],"lifetime":[53],"of":[54,87,97,107,120,138],"resistive":[55],"crossbar":[56],"As":[58],"case":[60],"study,":[61],"monitor":[63],"Programmable":[69],"Logic-in-Memory":[70],"(PLiM)":[71],"architecture,":[72],"and":[73,95,112,140,147],"propose":[74],"an":[75],"endurance":[76],"management":[77],"scheme":[78],"for":[79],"it.":[80],"The":[81],"proposed":[82],"endurance-aware":[83],"compilation":[84],"capable":[86],"handling":[88],"different":[89],"trade-offs":[90],"between":[91],"balance,":[93],"latency,":[94],"area":[96],"resulting":[99],"PLiM":[100],"implementations.":[101],"Experimental":[102],"evaluations":[103],"set":[106],"benchmarks":[108],"including":[109],"large":[110],"arithmetic":[111],"control":[113],"functions":[114],"show":[115],"that":[116],"standard":[118],"deviation":[119],"writes":[121],"can":[122],"reduced":[124],"by":[125,145],"86.65%":[126],"average":[128,136],"compared":[129],"naive":[132],"compiler,":[133],"while":[134],"number":[137],"instructions":[139],"RRAM":[141],"devices":[142],"also":[143],"decreases":[144],"36.45%":[146],"13.67%,":[148],"respectively.":[149]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":6}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
