{"id":"https://openalex.org/W2612907783","doi":"https://doi.org/10.23919/date.2017.7927151","title":"MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systems","display_name":"MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systems","publication_year":2017,"publication_date":"2017-03-01","ids":{"openalex":"https://openalex.org/W2612907783","doi":"https://doi.org/10.23919/date.2017.7927151","mag":"2612907783"},"language":"en","primary_location":{"id":"doi:10.23919/date.2017.7927151","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927151","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100368438","display_name":"Di Chen","orcid":"https://orcid.org/0000-0001-7873-4838"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Di Chen","raw_affiliation_strings":["Services Computing Technology and System Lab, Huazhong University of Science and Technology, Wuhan, China"],"affiliations":[{"raw_affiliation_string":"Services Computing Technology and System Lab, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022262922","display_name":"Hai Jin","orcid":"https://orcid.org/0000-0002-3934-7605"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hai Jin","raw_affiliation_strings":["Services Computing Technology and System Lab, Huazhong University of Science and Technology, Wuhan, China"],"affiliations":[{"raw_affiliation_string":"Services Computing Technology and System Lab, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022398389","display_name":"Xiaofei Liao","orcid":"https://orcid.org/0000-0001-6302-813X"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaofei Liao","raw_affiliation_strings":["Services Computing Technology and System Lab, Huazhong University of Science and Technology, Wuhan, China"],"affiliations":[{"raw_affiliation_string":"Services Computing Technology and System Lab, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033955608","display_name":"Haikun Liu","orcid":"https://orcid.org/0000-0003-4290-1408"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Haikun Liu","raw_affiliation_strings":["Services Computing Technology and System Lab, Huazhong University of Science and Technology, Wuhan, China"],"affiliations":[{"raw_affiliation_string":"Services Computing Technology and System Lab, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039473179","display_name":"Rentong Guo","orcid":null},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Rentong Guo","raw_affiliation_strings":["Services Computing Technology and System Lab, Huazhong University of Science and Technology, Wuhan, China"],"affiliations":[{"raw_affiliation_string":"Services Computing Technology and System Lab, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100407506","display_name":"Dong Liu","orcid":"https://orcid.org/0000-0003-0451-5979"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dong Liu","raw_affiliation_strings":["Services Computing Technology and System Lab, Huazhong University of Science and Technology, Wuhan, China"],"affiliations":[{"raw_affiliation_string":"Services Computing Technology and System Lab, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5100368438"],"corresponding_institution_ids":["https://openalex.org/I47720641"],"apc_list":null,"apc_paid":null,"fwci":2.2532,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.89332063,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1086","last_page":"1091"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8266195058822632},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6835719347000122},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.566405713558197},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.494260311126709},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48280656337738037},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.47510063648223877},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.46224474906921387},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.46090611815452576},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.42889994382858276},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.42423611879348755},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.39256900548934937},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3693721890449524},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3605383038520813},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.3517037034034729},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2680644392967224},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26514363288879395},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.23812779784202576}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8266195058822632},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6835719347000122},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.566405713558197},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.494260311126709},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48280656337738037},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.47510063648223877},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.46224474906921387},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.46090611815452576},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.42889994382858276},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.42423611879348755},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.39256900548934937},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3693721890449524},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3605383038520813},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.3517037034034729},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2680644392967224},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26514363288879395},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.23812779784202576}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date.2017.7927151","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927151","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8299999833106995,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1968029317","https://openalex.org/W1979955706","https://openalex.org/W1987367554","https://openalex.org/W2005887179","https://openalex.org/W2014561172","https://openalex.org/W2029577083","https://openalex.org/W2041420601","https://openalex.org/W2060397112","https://openalex.org/W2116394526","https://openalex.org/W2117788358","https://openalex.org/W2124350608","https://openalex.org/W2125428294","https://openalex.org/W2133059825","https://openalex.org/W2135965542","https://openalex.org/W2143773524","https://openalex.org/W2143835304","https://openalex.org/W2147657366","https://openalex.org/W2149412112","https://openalex.org/W2161511909","https://openalex.org/W2234174598","https://openalex.org/W4234169122","https://openalex.org/W6677472206"],"related_works":["https://openalex.org/W2217292995","https://openalex.org/W2115782696","https://openalex.org/W3145643808","https://openalex.org/W2966447112","https://openalex.org/W4321458411","https://openalex.org/W2363409354","https://openalex.org/W109043737","https://openalex.org/W2262128607","https://openalex.org/W4392546877","https://openalex.org/W2138789847"],"abstract_inverted_index":{"Current":[0,85],"DRAM":[1,27,59,114,170],"based":[2],"memory":[3,18,40,56,78,83,147],"systems":[4,41],"face":[5],"the":[6,52,107,130,153,190],"scalability":[7],"challenges":[8],"in":[9,62,81],"terms":[10],"of":[11,21,55,64,109,132,152,158],"storage":[12],"density,":[13],"power,":[14],"and":[15,26,34,60,115,117,161,189,198,201],"cost.":[16],"Hybrid":[17],"architecture":[19],"composed":[20],"emerging":[22],"Non-Volatile":[23],"Memory":[24,124],"(NVM)":[25],"is":[28,70,150],"a":[29,43,119,137],"promising":[30],"approach":[31],"to":[32,46,51,58,91,128,196],"large-capacity":[33],"energy-efficient":[35],"main":[36],"memory.":[37],"However,":[38],"hybrid":[39,82,133,146],"pose":[42],"new":[44],"challenge":[45],"on-chip":[47],"cache":[48,65,86,93,110,142],"management":[49],"due":[50],"asymmetrical":[53],"penalty":[54,112],"access":[57,79],"NVM":[61,164],"case":[63],"misses.":[66],"Cache":[67],"hit":[68,94],"rate":[69,95],"no":[71],"longer":[72],"an":[73],"effective":[74],"metric":[75],"for":[76,145],"evaluating":[77],"performance":[80,131,186],"systems.":[84,148],"replacement":[87,143],"policies":[88],"that":[89,182],"aim":[90],"improve":[92],"are":[96],"not":[97],"efficient":[98],"either.":[99],"In":[100],"this":[101],"paper,":[102],"we":[103],"take":[104],"into":[105],"account":[106],"asymmetry":[108],"miss":[111,138],"on":[113,203],"NVM,":[116],"advocate":[118],"more":[120],"general":[121],"metric,":[122],"Average":[123],"Access":[125],"Time":[126],"(AMAT),":[127],"evaluate":[129],"memories.":[134],"We":[135],"propose":[136],"penalty-aware":[139],"LRU-based":[140],"(MALRU)":[141],"policy":[144,193],"MALRU":[149,183],"aware":[151],"source":[154],"(DRAM":[155],"or":[156],"NVM)":[157],"missing":[159],"blocks":[160,165,171],"prevents":[162],"high-latency":[163],"as":[166,168],"well":[167],"low-latency":[169],"with":[172],"good":[173],"temporal":[174],"locality":[175],"from":[176],"being":[177],"evicted.":[178],"Experimental":[179],"results":[180],"show":[181],"improves":[184],"system":[185],"against":[187],"LRU":[188],"state-of-the-art":[191],"HAP":[192],"by":[194],"up":[195],"20.4%":[197],"11.7%":[199],"(11.1%":[200],"5.7%":[202],"average),":[204],"respectively.":[205]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":6},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}