{"id":"https://openalex.org/W2613010563","doi":"https://doi.org/10.23919/date.2017.7927106","title":"Analyzing the effects of peripheral circuit aging of embedded SRAM architectures","display_name":"Analyzing the effects of peripheral circuit aging of embedded SRAM architectures","publication_year":2017,"publication_date":"2017-03-01","ids":{"openalex":"https://openalex.org/W2613010563","doi":"https://doi.org/10.23919/date.2017.7927106","mag":"2613010563"},"language":"en","primary_location":{"id":"doi:10.23919/date.2017.7927106","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927106","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067545661","display_name":"Josef Kinseher","orcid":"https://orcid.org/0000-0001-6923-1059"},"institutions":[{"id":"https://openalex.org/I4210094487","display_name":"Intel (Germany)","ror":"https://ror.org/00m2x0g47","country_code":"DE","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210094487"]},{"id":"https://openalex.org/I186354981","display_name":"University of Passau","ror":"https://ror.org/05ydjnb78","country_code":"DE","type":"education","lineage":["https://openalex.org/I186354981"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Josef Kinseher","raw_affiliation_strings":["Intel Deutschland, Neubiberg, Germany","University of Passau, Passau, Germany"],"affiliations":[{"raw_affiliation_string":"Intel Deutschland, Neubiberg, Germany","institution_ids":["https://openalex.org/I4210094487"]},{"raw_affiliation_string":"University of Passau, Passau, Germany","institution_ids":["https://openalex.org/I186354981"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5098075439","display_name":"Leonhard Heiss","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094487","display_name":"Intel (Germany)","ror":"https://ror.org/00m2x0g47","country_code":"DE","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210094487"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Leonhard Heiss","raw_affiliation_strings":["Intel Deutschland, Neubiberg, Germany"],"affiliations":[{"raw_affiliation_string":"Intel Deutschland, Neubiberg, Germany","institution_ids":["https://openalex.org/I4210094487"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027416202","display_name":"Ilia Polian","orcid":"https://orcid.org/0000-0002-6563-2725"},"institutions":[{"id":"https://openalex.org/I186354981","display_name":"University of Passau","ror":"https://ror.org/05ydjnb78","country_code":"DE","type":"education","lineage":["https://openalex.org/I186354981"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ilia Polian","raw_affiliation_strings":["University of Passau, Passau, Germany"],"affiliations":[{"raw_affiliation_string":"University of Passau, Passau, Germany","institution_ids":["https://openalex.org/I186354981"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5067545661"],"corresponding_institution_ids":["https://openalex.org/I186354981","https://openalex.org/I4210094487"],"apc_list":null,"apc_paid":null,"fwci":1.7201,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.85271693,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"852","last_page":"857"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8900893926620483},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.6702820658683777},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.6624174118041992},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5802140831947327},{"id":"https://openalex.org/keywords/degradation","display_name":"Degradation (telecommunications)","score":0.5130195021629333},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.508721649646759},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.499631404876709},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4464883506298065},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4338008761405945},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3949067294597626},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3283630609512329},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28120025992393494},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24343708157539368},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2118849754333496},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11905837059020996}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8900893926620483},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.6702820658683777},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.6624174118041992},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5802140831947327},{"id":"https://openalex.org/C2779679103","wikidata":"https://www.wikidata.org/wiki/Q5251805","display_name":"Degradation (telecommunications)","level":2,"score":0.5130195021629333},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.508721649646759},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.499631404876709},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4464883506298065},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4338008761405945},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3949067294597626},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3283630609512329},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28120025992393494},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24343708157539368},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2118849754333496},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11905837059020996},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date.2017.7927106","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927106","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1582724633","https://openalex.org/W1988922865","https://openalex.org/W2057919563","https://openalex.org/W2082102392","https://openalex.org/W2100483769","https://openalex.org/W2102785080","https://openalex.org/W2112628818","https://openalex.org/W2113115586","https://openalex.org/W2118168173","https://openalex.org/W2122757690","https://openalex.org/W2137706187","https://openalex.org/W2150220758","https://openalex.org/W2153355333","https://openalex.org/W2486425261","https://openalex.org/W2542799880","https://openalex.org/W2545401637"],"related_works":["https://openalex.org/W1835913819","https://openalex.org/W2051363901","https://openalex.org/W2127348582","https://openalex.org/W2136142653","https://openalex.org/W2373152541","https://openalex.org/W2174410816","https://openalex.org/W2548084981","https://openalex.org/W2189053673","https://openalex.org/W3200702775","https://openalex.org/W2186356227"],"abstract_inverted_index":{"Modern":[0],"System-on-Chips":[1],"rely":[2],"heavily":[3],"on":[4,157],"the":[5,17,32,38,59,76,79,83,117,145,158,169],"performance":[6,65],"of":[7,21,34,41,58,67,78,104,113,119,133,148,160],"their":[8],"embedded":[9,162],"memories":[10],"which":[11],"are":[12],"also":[13],"most":[14],"susceptible":[15],"to":[16,29,93,101,171],"increasing":[18],"reliability":[19],"challenges":[20],"today's":[22],"nanoscale":[23],"technology":[24],"nodes.":[25],"However,":[26],"in":[27,111,142],"contrast":[28],"memory":[30,71,96,163],"core-cells,":[31],"effects":[33,125],"transistor":[35],"aging":[36,124,173],"inside":[37,126],"peripheral":[39,60,80,134],"logic":[40,81],"SRAM":[42,61,120],"architectures":[43],"have":[44],"received":[45],"little":[46],"attention.":[47],"This":[48],"study":[49,166],"works":[50],"out":[51],"how":[52],"BTI":[53],"and":[54,99,128],"HCI":[55],"induced":[56],"wear-out":[57,132],"circuitry":[62,122,135],"impacts":[63],"various":[64],"metrics":[66],"an":[68,161],"industrially":[69],"used":[70],"library.":[72],"We":[73,107],"show":[74,109],"that":[75,110],"degradation":[77,118],"is":[82,150],"dominant":[84],"driver":[85],"for":[86,180],"access":[87,114,139],"speed":[88],"loss":[89],"while":[90],"it":[91],"tends":[92],"slightly":[94],"lower":[95,152],"read":[97],"margin":[98,116,141],"lead":[100],"minor":[102],"improvements":[103],"write":[105],"margin.":[106],"furthermore":[108],"terms":[112],"time":[115,140],"control":[121],"counteracts":[123],"core-cells":[127],"sense":[129],"amplifiers.":[130],"Surprisingly,":[131],"can":[136],"even":[137],"improve":[138],"case":[143],"when":[144],"relative":[146],"magnitude":[147],"PBTI":[149],"much":[151],"compared":[153],"with":[154],"NBTI.":[155],"Based":[156],"example":[159],"library,":[164],"this":[165],"further":[167],"underlines":[168],"importance":[170],"analyze":[172],"mechanisms":[174],"at":[175],"system":[176],"level":[177],"rather":[178],"than":[179],"its":[181],"individual":[182],"interacting":[183],"sub-circuits.":[184]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":7},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}