{"id":"https://openalex.org/W2525382741","doi":"https://doi.org/10.23919/date.2017.7927080","title":"Automating the pipeline of arithmetic datapaths","display_name":"Automating the pipeline of arithmetic datapaths","publication_year":2017,"publication_date":"2017-03-01","ids":{"openalex":"https://openalex.org/W2525382741","doi":"https://doi.org/10.23919/date.2017.7927080","mag":"2525382741"},"language":"en","primary_location":{"id":"doi:10.23919/date.2017.7927080","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927080","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088622873","display_name":"Matei Istoan","orcid":"https://orcid.org/0000-0003-0960-1059"},"institutions":[{"id":"https://openalex.org/I100532134","display_name":"Universit\u00e9 Claude Bernard Lyon 1","ror":"https://ror.org/029brtt94","country_code":"FR","type":"education","lineage":["https://openalex.org/I100532134","https://openalex.org/I203339264"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Matei Istoan","raw_affiliation_strings":["Univ Lyon, CITI, France"],"affiliations":[{"raw_affiliation_string":"Univ Lyon, CITI, France","institution_ids":["https://openalex.org/I100532134"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035966925","display_name":"Florent de Dinechin","orcid":"https://orcid.org/0000-0003-4927-3301"},"institutions":[{"id":"https://openalex.org/I100532134","display_name":"Universit\u00e9 Claude Bernard Lyon 1","ror":"https://ror.org/029brtt94","country_code":"FR","type":"education","lineage":["https://openalex.org/I100532134","https://openalex.org/I203339264"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Florent de Dinechin","raw_affiliation_strings":["Univ Lyon, CITI, France"],"affiliations":[{"raw_affiliation_string":"Univ Lyon, CITI, France","institution_ids":["https://openalex.org/I100532134"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5088622873"],"corresponding_institution_ids":["https://openalex.org/I100532134"],"apc_list":null,"apc_paid":null,"fwci":0.52855561,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.67889525,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"704","last_page":"709"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9205567836761475},{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.8941696882247925},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8112349510192871},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.8064462542533875},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6578982472419739},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5890229940414429},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5801418423652649},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4467952251434326},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.44678768515586853},{"id":"https://openalex.org/keywords/software-pipelining","display_name":"Software pipelining","score":0.4348013401031494},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.418666273355484},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.39498627185821533},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2549203038215637},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.11326685547828674},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0957116186618805}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9205567836761475},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.8941696882247925},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8112349510192871},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.8064462542533875},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6578982472419739},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5890229940414429},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5801418423652649},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4467952251434326},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.44678768515586853},{"id":"https://openalex.org/C188854837","wikidata":"https://www.wikidata.org/wiki/Q268469","display_name":"Software pipelining","level":3,"score":0.4348013401031494},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.418666273355484},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.39498627185821533},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2549203038215637},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.11326685547828674},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0957116186618805},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/date.2017.7927080","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927080","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.49000000953674316}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1953836601","https://openalex.org/W2018758602","https://openalex.org/W2030898836","https://openalex.org/W2056616949","https://openalex.org/W2087656024","https://openalex.org/W2126779549","https://openalex.org/W2524070232","https://openalex.org/W4250147604","https://openalex.org/W6640945216"],"related_works":["https://openalex.org/W1819235735","https://openalex.org/W2155325307","https://openalex.org/W2155582075","https://openalex.org/W1910608351","https://openalex.org/W4256142740","https://openalex.org/W1519734376","https://openalex.org/W2036863757","https://openalex.org/W1869918998","https://openalex.org/W4241609064","https://openalex.org/W2110618453"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"the":[3,18,55,88,91,95,99,109],"new":[4],"framework":[5],"for":[6,35],"semi-automatic":[7],"circuit":[8,100],"pipelining":[9,82],"that":[10,106],"will":[11],"be":[12],"used":[13],"in":[14],"future":[15],"releases":[16],"of":[17,25,39,46,53,57,94],"FloPoCo":[19],"generator.":[20],"From":[21],"a":[22,36,43],"single":[23],"description":[24],"an":[26],"operator":[27],"or":[28],"datapath,":[29],"optimized":[30],"implementations":[31],"are":[32],"obtained":[33],"automatically":[34],"wide":[37,44],"range":[38,45],"FPGA":[40],"targets":[41],"and":[42,68],"frequency/latency":[47],"trade-offs.":[48],"Compared":[49],"to":[50],"previous":[51],"versions":[52],"FloPoCo,":[54],"level":[56],"abstraction":[58],"has":[59],"been":[60],"raised,":[61],"enabling":[62],"easier":[63],"development,":[64],"shorter":[65],"generator":[66],"code,":[67],"better":[69],"pipeline":[70,96],"optimization.":[71],"The":[72],"proposed":[73,89],"approach":[74],"is":[75],"also":[76],"more":[77],"flexible":[78],"than":[79],"fully":[80],"automatic":[81],"approaches":[83],"based":[84],"on":[85,108],"retiming:":[86],"In":[87],"technique,":[90],"incremental":[92],"construction":[93],"along":[97],"with":[98],"graph":[101],"enables":[102],"architectural":[103],"design":[104],"decisions":[105],"depend":[107],"pipeline.":[110]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}