{"id":"https://openalex.org/W2611982830","doi":"https://doi.org/10.23919/date.2017.7927025","title":"Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project","display_name":"Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project","publication_year":2017,"publication_date":"2017-03-01","ids":{"openalex":"https://openalex.org/W2611982830","doi":"https://doi.org/10.23919/date.2017.7927025","mag":"2611982830"},"language":"en","primary_location":{"id":"doi:10.23919/date.2017.7927025","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927025","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008834768","display_name":"Marco Rabozzi","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"M. Rabozzi","raw_affiliation_strings":["Politecnico di Milano, DEIB, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, DEIB, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003093233","display_name":"Giuseppe Natale","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Natale","raw_affiliation_strings":["Politecnico di Milano, DEIB, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, DEIB, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083420180","display_name":"Emanuele Del Sozzo","orcid":"https://orcid.org/0000-0003-3101-8118"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"E. Del Sozzo","raw_affiliation_strings":["Politecnico di Milano, DEIB, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, DEIB, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025756141","display_name":"Alberto Scolari","orcid":"https://orcid.org/0000-0002-5862-8787"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Scolari","raw_affiliation_strings":["Politecnico di Milano, DEIB, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, DEIB, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085232708","display_name":"Luca Stornaiuolo","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Stornaiuolo","raw_affiliation_strings":["Politecnico di Milano, DEIB, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, DEIB, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010543929","display_name":"Marco D. Santambrogio","orcid":"https://orcid.org/0000-0002-9883-9693"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. D. Santambrogio","raw_affiliation_strings":["Politecnico di Milano, DEIB, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, DEIB, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5008834768"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":1.1266,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.7793785,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"33","issue":null,"first_page":"410","last_page":"415"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/supercomputer","display_name":"Supercomputer","score":0.8450103998184204},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6633192896842957},{"id":"https://openalex.org/keywords/exascale-computing","display_name":"Exascale computing","score":0.6366512179374695},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.5879255533218384},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44679170846939087},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3795924186706543},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.34700512886047363},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.149196058511734},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11903038620948792}],"concepts":[{"id":"https://openalex.org/C83283714","wikidata":"https://www.wikidata.org/wiki/Q121117","display_name":"Supercomputer","level":2,"score":0.8450103998184204},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6633192896842957},{"id":"https://openalex.org/C2778837361","wikidata":"https://www.wikidata.org/wiki/Q2450880","display_name":"Exascale computing","level":3,"score":0.6366512179374695},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.5879255533218384},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44679170846939087},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3795924186706543},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.34700512886047363},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.149196058511734},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11903038620948792}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.23919/date.2017.7927025","is_oa":false,"landing_page_url":"https://doi.org/10.23919/date.2017.7927025","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/1032008","is_oa":false,"landing_page_url":"http://ieeexplore.ieee.org/document/7927025/","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W594283781","https://openalex.org/W1980208272","https://openalex.org/W1987873989","https://openalex.org/W2006312753","https://openalex.org/W2010556856","https://openalex.org/W2036887984","https://openalex.org/W2056199026","https://openalex.org/W2070961300","https://openalex.org/W2072505467","https://openalex.org/W2078204120","https://openalex.org/W2087064593","https://openalex.org/W2098335003","https://openalex.org/W2130097981","https://openalex.org/W2170049777","https://openalex.org/W2221279259","https://openalex.org/W2280749311","https://openalex.org/W2324706433","https://openalex.org/W2399857432","https://openalex.org/W2512096148","https://openalex.org/W2538589664","https://openalex.org/W2598480883","https://openalex.org/W4255560897","https://openalex.org/W6651700774","https://openalex.org/W6712694180"],"related_works":["https://openalex.org/W1599154403","https://openalex.org/W4318068934","https://openalex.org/W2290952066","https://openalex.org/W2056528600","https://openalex.org/W3128098196","https://openalex.org/W4320480730","https://openalex.org/W4297752063","https://openalex.org/W2572977084","https://openalex.org/W1989530240","https://openalex.org/W2346596560"],"abstract_inverted_index":{"Since":[0],"the":[1,8,36,51,103,109],"end":[2],"of":[3,10,55,102],"Moore's":[4],"law":[5],"is":[6,38],"limiting":[7],"growth":[9],"general":[11],"purpose":[12],"processors,":[13],"High":[14],"Performance":[15],"Processing":[16],"(HPC)":[17],"systems":[18,78],"are":[19],"considering":[20],"FPGA-based":[21],"accelerators":[22],"as":[23],"a":[24,67],"promising":[25],"solution":[26],"for":[27],"several":[28,116],"application":[29],"fields.":[30],"However,":[31],"their":[32,97],"employment":[33],"poses":[34],"challenges":[35],"research":[37,126],"still":[39],"tackling,":[40],"and":[41,44,53,61,87,95,112,123],"existing":[42],"tools":[43],"workflows":[45],"do":[46],"not":[47],"naturally":[48],"adapt":[49],"to":[50,76,82,93,119],"scale":[52],"complexity":[54],"HPC":[56,77],"domains.":[57],"To":[58],"help":[59],"researchers":[60,86],"practitioners,":[62],"this":[63],"paper":[64,107],"proposes":[65],"CAOS,":[66],"platform":[68],"that":[69],"implements":[70],"an":[71],"FPGA":[72],"development":[73],"workflow":[74,111],"tailored":[75],"while":[79],"being":[80],"open":[81],"external":[83],"contributions.":[84,127],"Indeed,":[85],"developers":[88],"can":[89],"plug":[90],"into":[91],"CAOS":[92,110],"experiment":[94],"compare":[96],"solutions":[98],"at":[99],"each":[100],"step":[101],"design":[104],"flow.":[105],"This":[106],"describes":[108],"validates":[113],"it":[114],"against":[115],"case":[117],"studies":[118],"assess":[120],"its":[121],"generality":[122],"highlight":[124],"possible":[125]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}