{"id":"https://openalex.org/W2264681025","doi":"https://doi.org/10.2312/eggh/eggh96/025-037","title":"An Advanced 3D Frame Buffer Memory Controller","display_name":"An Advanced 3D Frame Buffer Memory Controller","publication_year":1996,"publication_date":"1996-01-01","ids":{"openalex":"https://openalex.org/W2264681025","doi":"https://doi.org/10.2312/eggh/eggh96/025-037","mag":"2264681025"},"language":"en","primary_location":{"id":"doi:10.2312/eggh/eggh96/025-037","is_oa":true,"landing_page_url":"https://doi.org/10.2312/eggh/eggh96/025-037","pdf_url":null,"source":{"id":"https://openalex.org/S7407052899","display_name":"Eurographics","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"article"},"type":"article","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.2312/eggh/eggh96/025-037","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004780292","display_name":"Alex Makris","orcid":null},"institutions":[{"id":"https://openalex.org/I162608824","display_name":"University of Sussex","ror":"https://ror.org/00ayhx656","country_code":"GB","type":"education","lineage":["https://openalex.org/I162608824"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Makris, \"Alex","raw_affiliation_strings":["Centre for VLSI and Computer Graphics, School of Engineering, University of Sussex, Brighton, UK#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for VLSI and Computer Graphics, School of Engineering, University of Sussex, Brighton, UK#TAB#","institution_ids":["https://openalex.org/I162608824"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052669359","display_name":"Martin White","orcid":"https://orcid.org/0000-0001-8686-2274"},"institutions":[{"id":"https://openalex.org/I162608824","display_name":"University of Sussex","ror":"https://ror.org/00ayhx656","country_code":"GB","type":"education","lineage":["https://openalex.org/I162608824"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"White, Martin","raw_affiliation_strings":["Centre for VLSI and Computer Graphics, School of Engineering, University of Sussex, Brighton, UK#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for VLSI and Computer Graphics, School of Engineering, University of Sussex, Brighton, UK#TAB#","institution_ids":["https://openalex.org/I162608824"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090688904","display_name":"Paul Lister","orcid":null},"institutions":[{"id":"https://openalex.org/I162608824","display_name":"University of Sussex","ror":"https://ror.org/00ayhx656","country_code":"GB","type":"education","lineage":["https://openalex.org/I162608824"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Lister\", Paul","raw_affiliation_strings":["Centre for VLSI and Computer Graphics, School of Engineering, University of Sussex, Brighton, UK#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for VLSI and Computer Graphics, School of Engineering, University of Sussex, Brighton, UK#TAB#","institution_ids":["https://openalex.org/I162608824"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I162608824"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"25","last_page":"37"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9943000078201294,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9943000078201294,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9927999973297119,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9879999756813049,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.8293842077255249},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7516380548477173},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.6637481451034546},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.6587061285972595},{"id":"https://openalex.org/keywords/interleaving","display_name":"Interleaving","score":0.6314979791641235},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.559586226940155},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.5013983249664307},{"id":"https://openalex.org/keywords/frame","display_name":"Frame (networking)","score":0.4968254864215851},{"id":"https://openalex.org/keywords/raster-graphics","display_name":"Raster graphics","score":0.49192214012145996},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.48507633805274963},{"id":"https://openalex.org/keywords/byte","display_name":"Byte","score":0.45596593618392944},{"id":"https://openalex.org/keywords/write-buffer","display_name":"Write buffer","score":0.4445028305053711},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.4182007312774658},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4145960807800293},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40759867429733276},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.35857415199279785},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3297651410102844},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.24766674637794495},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.24578991532325745},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.22723901271820068},{"id":"https://openalex.org/keywords/computer-graphics","display_name":"Computer graphics (images)","score":0.15777525305747986},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.11589539051055908},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08478778600692749}],"concepts":[{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.8293842077255249},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7516380548477173},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.6637481451034546},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.6587061285972595},{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.6314979791641235},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.559586226940155},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.5013983249664307},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.4968254864215851},{"id":"https://openalex.org/C181844469","wikidata":"https://www.wikidata.org/wiki/Q182270","display_name":"Raster graphics","level":2,"score":0.49192214012145996},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.48507633805274963},{"id":"https://openalex.org/C43364308","wikidata":"https://www.wikidata.org/wiki/Q8799","display_name":"Byte","level":2,"score":0.45596593618392944},{"id":"https://openalex.org/C89089495","wikidata":"https://www.wikidata.org/wiki/Q8038418","display_name":"Write buffer","level":5,"score":0.4445028305053711},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.4182007312774658},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4145960807800293},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40759867429733276},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.35857415199279785},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3297651410102844},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.24766674637794495},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.24578991532325745},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.22723901271820068},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.15777525305747986},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.11589539051055908},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08478778600692749},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.2312/eggh/eggh96/025-037","is_oa":true,"landing_page_url":"https://doi.org/10.2312/eggh/eggh96/025-037","pdf_url":null,"source":{"id":"https://openalex.org/S7407052899","display_name":"Eurographics","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article"},{"id":"mag:2264681025","is_oa":false,"landing_page_url":"https://diglib.eg.org/bitstream/handle/10.2312/EGGH.EGGH96.025-037/025-037.pdf;sequence=1","pdf_url":null,"source":{"id":"https://openalex.org/S4306418297","display_name":"Eurographics Conference on Graphics Hardware","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":"Eurographics Conference on Graphics Hardware","raw_type":null}],"best_oa_location":{"id":"doi:10.2312/eggh/eggh96/025-037","is_oa":true,"landing_page_url":"https://doi.org/10.2312/eggh/eggh96/025-037","pdf_url":null,"source":{"id":"https://openalex.org/S7407052899","display_name":"Eurographics","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"article"},"sustainable_development_goals":[{"score":0.5299999713897705,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2801746350","https://openalex.org/W2832716989","https://openalex.org/W773491645","https://openalex.org/W2084310805","https://openalex.org/W1548956582","https://openalex.org/W1986267675","https://openalex.org/W2142110652","https://openalex.org/W2433234826","https://openalex.org/W2826445944","https://openalex.org/W57947696","https://openalex.org/W3091006527","https://openalex.org/W2405565196","https://openalex.org/W165439516","https://openalex.org/W1941867030","https://openalex.org/W2030008627","https://openalex.org/W2405146573","https://openalex.org/W2394659129","https://openalex.org/W649366328","https://openalex.org/W2140752397","https://openalex.org/W2142571940"],"abstract_inverted_index":{"This":[0,25,64],"paper":[1],"details":[2],"the":[3],"design":[4],"o":[5,34,60,120,127],"f":[6,35,61,121,128],"an":[7],"advanced":[8],"32":[9],"bit":[10],"3D":[11,18,84,93],"frame":[12,77],"buffer":[13,78],"memory":[14,26,94,129],"controller":[15,27,95],"for":[16,38,45,51],"a":[17,32,57],"Graphics":[19],"Raster":[20],"Processor":[21],"called":[22],"TAYRA":[23],"[1].":[24],"is":[28,66,96],"designed":[29,97],"to":[30,98,114,131],"provide":[31],"performance":[33,65],"33":[36],"MPixelsls":[37,50],"read":[39],"and":[40,48,89,102,104,124],"write":[41,54],"cycles,":[42],"4":[43,62,115],"GPixelsls":[44],"block":[46],"write,":[47],"16.5":[49],"read,":[52],"modify,":[53],"cycles":[55],"(with":[56],"pixel":[58],"size":[59],"bytes).":[63],"without":[67],"any":[68],"interleaving.":[69],"It":[70],"has":[71],"several":[72],"control":[73,99],"modes:":[74],"S3":[75],"shared":[76],"protocol":[79],"compatibility":[80],"[2],":[81],"stand":[82],"alone":[83],"buffers,":[85,88,117],"multiplexed":[86],"2DI3D":[87],"others.":[90],"Further,":[91],"our":[92],"DRAM,":[100],"VRAM":[101],"WRAM,":[103],"EDO":[105],"versions":[106],"of":[107],"these":[108],"memories.":[109],"Also,":[110],"we":[111],"support":[112],"up":[113],"screen":[116,122],"16":[118],"MBytes":[119],"memory,":[123],"many":[125],"combinations":[126],"organisationsup":[130],"1600x1280.":[132]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}