{"id":"https://openalex.org/W6945016056","doi":"https://doi.org/10.2312/eggh/eggh07/065-072","title":"A Real-Time FPGA-Based Architecture for a Reinhard-like Tone Mapping Operator","display_name":"A Real-Time FPGA-Based Architecture for a Reinhard-like Tone Mapping Operator","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W6945016056","doi":"https://doi.org/10.2312/eggh/eggh07/065-072"},"language":"en","primary_location":{"id":"doi:10.2312/eggh/eggh07/065-072","is_oa":true,"landing_page_url":"https://doi.org/10.2312/eggh/eggh07/065-072","pdf_url":null,"source":{"id":"https://openalex.org/S7407052899","display_name":"Eurographics","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"article"},"type":"other","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.2312/eggh/eggh07/065-072","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Hassan, F.","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hassan, F.","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":null,"display_name":"Carletta, J. E.","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Carletta, J. E.","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":true,"primary_topic":null,"topics":[],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7806000113487244},{"id":"https://openalex.org/keywords/operator","display_name":"Operator (biology)","score":0.6096000075340271},{"id":"https://openalex.org/keywords/frame","display_name":"Frame (networking)","score":0.5856000185012817},{"id":"https://openalex.org/keywords/tone-mapping","display_name":"Tone mapping","score":0.5551999807357788},{"id":"https://openalex.org/keywords/tone","display_name":"Tone (literature)","score":0.5497000217437744},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5092999935150146},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.508899986743927}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7806000113487244},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6723999977111816},{"id":"https://openalex.org/C17020691","wikidata":"https://www.wikidata.org/wiki/Q139677","display_name":"Operator (biology)","level":5,"score":0.6096000075340271},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.5856000185012817},{"id":"https://openalex.org/C8641274","wikidata":"https://www.wikidata.org/wiki/Q1030958","display_name":"Tone mapping","level":4,"score":0.5551999807357788},{"id":"https://openalex.org/C2780583480","wikidata":"https://www.wikidata.org/wiki/Q1366327","display_name":"Tone (literature)","level":2,"score":0.5497000217437744},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5351999998092651},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5092999935150146},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.508899986743927},{"id":"https://openalex.org/C3261483","wikidata":"https://www.wikidata.org/wiki/Q119565","display_name":"Frame rate","level":2,"score":0.5011000037193298},{"id":"https://openalex.org/C98025372","wikidata":"https://www.wikidata.org/wiki/Q477538","display_name":"Systems architecture","level":3,"score":0.3409000039100647},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.31220000982284546},{"id":"https://openalex.org/C2779530757","wikidata":"https://www.wikidata.org/wiki/Q1207505","display_name":"Quality (philosophy)","level":2,"score":0.3100000023841858},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3091999888420105},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.29319998621940613},{"id":"https://openalex.org/C2221639","wikidata":"https://www.wikidata.org/wiki/Q2877","display_name":"Discrete cosine transform","level":3,"score":0.2775000035762787},{"id":"https://openalex.org/C134765980","wikidata":"https://www.wikidata.org/wiki/Q879126","display_name":"Bitwise operation","level":2,"score":0.26809999346733093},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2590000033378601},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.25380000472068787},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.2515999972820282},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.2502000033855438}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.2312/eggh/eggh07/065-072","is_oa":true,"landing_page_url":"https://doi.org/10.2312/eggh/eggh07/065-072","pdf_url":null,"source":{"id":"https://openalex.org/S7407052899","display_name":"Eurographics","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article"}],"best_oa_location":{"id":"doi:10.2312/eggh/eggh07/065-072","is_oa":true,"landing_page_url":"https://doi.org/10.2312/eggh/eggh07/065-072","pdf_url":null,"source":{"id":"https://openalex.org/S7407052899","display_name":"Eurographics","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,10,55,64],"field-programmable":[4],"gate":[5],"array-based":[6],"hardware":[7],"architecture":[8,35],"for":[9,63],"Reinhard-like":[11],"tone":[12],"mapping":[13],"operator.":[14],"Modifications":[15],"to":[16,23,30],"the":[17,26,72],"original":[18],"Reinhard":[19],"operator":[20,27],"were":[21],"done":[22],"ensure":[24],"that":[25],"is":[28,36,74],"amenable":[29],"implementation":[31,73],"in":[32,38],"hardware.":[33],"The":[34,69],"described":[37],"VHDL":[39],"and":[40],"has":[41],"been":[42],"synthesized":[43],"using":[44,76],"Altera":[45],"Quartus":[46],"tools.":[47],"It":[48],"achieves":[49],"an":[50],"operating":[51],"frequency":[52],"consistent":[53],"with":[54],"video":[56],"rate":[57],"of":[58,66,71],"60":[59],"frames":[60],"per":[61],"second":[62],"frame":[65],"1024\u00d7768":[67],"pixels.":[68],"quality":[70],"measured":[75],"peak":[77],"signal-tonoise":[78],"ratios":[79],"on":[80],"testbench":[81],"images.":[82]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
