{"id":"https://openalex.org/W4416932532","doi":"https://doi.org/10.1631/fitee.2400941","title":"Vina-FPGA2: a high-level parallelized hardware-accelerated molecular docking tool based on the inter-module pipeline","display_name":"Vina-FPGA2: a high-level parallelized hardware-accelerated molecular docking tool based on the inter-module pipeline","publication_year":2025,"publication_date":"2025-11-01","ids":{"openalex":"https://openalex.org/W4416932532","doi":"https://doi.org/10.1631/fitee.2400941"},"language":"en","primary_location":{"id":"doi:10.1631/fitee.2400941","is_oa":false,"landing_page_url":"https://doi.org/10.1631/fitee.2400941","pdf_url":null,"source":{"id":"https://openalex.org/S4210189857","display_name":"Frontiers of Information Technology & Electronic Engineering","issn_l":"2095-9184","issn":["2095-9184","2095-9230"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Frontiers of Information Technology &amp; Electronic Engineering","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078395317","display_name":"Ming Ling","orcid":"https://orcid.org/0000-0002-8866-7189"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Ming Ling","raw_affiliation_strings":["School of Integrated Circuits, Southeast University, Nanjing, 210096, China"],"raw_orcid":"https://orcid.org/0000-0002-8866-7189","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Southeast University, Nanjing, 210096, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087976552","display_name":"Shidi Tang","orcid":"https://orcid.org/0000-0001-5493-7411"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shidi Tang","raw_affiliation_strings":["School of Integrated Circuits, Southeast University, Nanjing, 210096, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Southeast University, Nanjing, 210096, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100761386","display_name":"Ruiqi Chen","orcid":"https://orcid.org/0000-0001-6837-5675"},"institutions":[{"id":"https://openalex.org/I13469542","display_name":"Vrije Universiteit Brussel","ror":"https://ror.org/006e5kg04","country_code":"BE","type":"education","lineage":["https://openalex.org/I13469542"]}],"countries":["BE"],"is_corresponding":true,"raw_author_name":"Ruiqi Chen","raw_affiliation_strings":["Department of Electronics and Informatics, Vrije Universiteit Brussel, Brussels, 1050, Belgium"],"raw_orcid":"https://orcid.org/0000-0001-6837-5675","affiliations":[{"raw_affiliation_string":"Department of Electronics and Informatics, Vrije Universiteit Brussel, Brussels, 1050, Belgium","institution_ids":["https://openalex.org/I13469542"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100354072","display_name":"Xin Li","orcid":"https://orcid.org/0000-0003-4257-4347"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xin Li","raw_affiliation_strings":["School of Integrated Circuits, Southeast University, Nanjing, 210096, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Southeast University, Nanjing, 210096, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055272142","display_name":"Yanxiang Zhu","orcid":"https://orcid.org/0000-0002-5014-3419"},"institutions":[{"id":"https://openalex.org/I4210090460","display_name":"Nanjing Institute of Railway Technology","ror":"https://ror.org/00ctyfm67","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210090460"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yanxiang Zhu","raw_affiliation_strings":["VeriMake Innovation Laboratory, Nanjing Renmian Integrated Circuit Company Ltd., Nanjing, 210088, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VeriMake Innovation Laboratory, Nanjing Renmian Integrated Circuit Company Ltd., Nanjing, 210088, China","institution_ids":["https://openalex.org/I4210090460"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5078395317","https://openalex.org/A5100761386"],"corresponding_institution_ids":["https://openalex.org/I13469542","https://openalex.org/I76569877"],"apc_list":{"value":2990,"currency":"USD","value_usd":2990},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.23234403,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"26","issue":"11","first_page":"2215","last_page":"2230"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.2597000002861023,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.2597000002861023,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.17270000278949738,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.13279999792575836,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.682699978351593},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.6643000245094299},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.5842000246047974},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.5112000107765198},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4156000018119812},{"id":"https://openalex.org/keywords/nested-loop-join","display_name":"Nested loop join","score":0.398499995470047},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.3725999891757965},{"id":"https://openalex.org/keywords/pipeline-transport","display_name":"Pipeline transport","score":0.3564999997615814}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7192999720573425},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.682699978351593},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.6643000245094299},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.5842000246047974},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5544999837875366},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.5112000107765198},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4156000018119812},{"id":"https://openalex.org/C1306188","wikidata":"https://www.wikidata.org/wiki/Q4060687","display_name":"Nested loop join","level":2,"score":0.398499995470047},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.3725999891757965},{"id":"https://openalex.org/C175309249","wikidata":"https://www.wikidata.org/wiki/Q725864","display_name":"Pipeline transport","level":2,"score":0.3564999997615814},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34310001134872437},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3287999927997589},{"id":"https://openalex.org/C35651441","wikidata":"https://www.wikidata.org/wiki/Q625303","display_name":"Independence (probability theory)","level":2,"score":0.3239000141620636},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.31349998712539673},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3061999976634979},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.28839999437332153},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.2842000126838684},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.27390000224113464},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2736000120639801},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.26260000467300415},{"id":"https://openalex.org/C48262172","wikidata":"https://www.wikidata.org/wiki/Q16908765","display_name":"Design process","level":3,"score":0.26249998807907104},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2614000141620636},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2547000050544739},{"id":"https://openalex.org/C159694833","wikidata":"https://www.wikidata.org/wiki/Q2321565","display_name":"Iterative method","level":2,"score":0.2526000142097473}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1631/fitee.2400941","is_oa":false,"landing_page_url":"https://doi.org/10.1631/fitee.2400941","pdf_url":null,"source":{"id":"https://openalex.org/S4210189857","display_name":"Frontiers of Information Technology & Electronic Engineering","issn_l":"2095-9184","issn":["2095-9184","2095-9230"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Frontiers of Information Technology &amp; Electronic Engineering","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W1983194490","https://openalex.org/W2014952106","https://openalex.org/W2024060531","https://openalex.org/W2055835086","https://openalex.org/W2108389384","https://openalex.org/W2130479394","https://openalex.org/W2132617221","https://openalex.org/W2134967712","https://openalex.org/W2141088024","https://openalex.org/W2159800085","https://openalex.org/W2170711116","https://openalex.org/W2613685575","https://openalex.org/W2768092025","https://openalex.org/W2844503360","https://openalex.org/W2888400067","https://openalex.org/W2895540242","https://openalex.org/W2902812092","https://openalex.org/W2907463061","https://openalex.org/W2917675277","https://openalex.org/W3010016408","https://openalex.org/W3078690673","https://openalex.org/W3114271647","https://openalex.org/W3120361527","https://openalex.org/W3159160110","https://openalex.org/W3168430821","https://openalex.org/W4280550952","https://openalex.org/W4296830446","https://openalex.org/W4312669283","https://openalex.org/W4328048996","https://openalex.org/W4387609137","https://openalex.org/W4393578753","https://openalex.org/W4394805339","https://openalex.org/W4397042806","https://openalex.org/W4399731549","https://openalex.org/W4408712111"],"related_works":[],"abstract_inverted_index":{"AutoDock":[0],"Vina":[1,69,88],"(Vina)":[2],"is":[3,27,66],"a":[4,13,18,43,179,192,216,226],"widely":[5],"adopted":[6],"molecular":[7],"docking":[8,51],"tool,":[9],"often":[10],"regarded":[11],"as":[12,17,40,173],"standard":[14],"or":[15],"used":[16],"baseline":[19],"in":[20,57,73,229],"numerous":[21],"studies.":[22],"However,":[23,53],"its":[24],"computational":[25,135],"process":[26],"highly":[28],"time-consuming.":[29],"The":[30],"pioneering":[31],"field-programmable":[32],"gate":[33],"array":[34],"(FPGA)-based":[35],"accelerator":[36],"of":[37,76],"Vina,":[38],"known":[39],"Vina-FPGA,":[41],"offers":[42],"high":[44],"energy-efficiency":[45],"approach":[46],"to":[47,68,110,165,222],"speed":[48],"up":[49],"the":[50,54,58,74,90,155,184,210],"process.":[52],"computation":[55,114,144],"modules":[56],"Vina-FPGA":[59],"design":[60,126,153],"are":[61],"not":[62],"efficiently":[63],"used.":[64],"This":[65,105],"due":[67],"exhibiting":[70],"irregular":[71],"behaviors":[72],"form":[75],"nested":[77],"loops":[78],"with":[79],"changing":[80],"upper":[81],"bounds":[82],"and":[83,159,177,215],"differing":[84],"control":[85],"flows.":[86],"Fortunately,":[87],"employs":[89],"Monte":[91],"Carlo":[92],"iterative":[93],"search":[94],"method,":[95],"which":[96],"requires":[97],"independent":[98],"computations":[99],"for":[100,127],"different":[101],"random":[102],"initial":[103],"inputs.":[104],"characteristic":[106],"provides":[107],"an":[108,123,149,174,204],"opportunity":[109],"implement":[111,148],"further":[112,128],"parallel":[113,152],"designs.":[115],"To":[116],"this":[117,119,189],"end,":[118],"paper":[120],"proposes":[121],"Vina-FPGA2,":[122],"inter-module":[124,150],"pipeline":[125,151],"accelerating":[129],"Vina-FPGA.":[130,220],"First,":[131],"we":[132,147,170],"use":[133],"individual":[134],"task":[136],"(Task)":[137],"independence":[138],"by":[139,154],"sequentially":[140],"filling":[141],"Tasks":[142],"into":[143],"modules.":[145],"Then,":[146],"Tag":[156],"Checker":[157],"module":[158],"architectural":[160],"modifications,":[161],"named":[162,196],"Vina-FPGA2-Baseline.":[163],"Next,":[164],"achieve":[166],"resource-efficient":[167],"hardware":[168],"implementation,":[169,195],"describe":[171],"it":[172],"optimization":[175],"problem":[176],"develop":[178],"reinforcement":[180],"learning-based":[181],"solver.":[182],"Targeting":[183],"Xilinx":[185],"UltraScale":[186],"XCKU060":[187],"platform,":[188],"solver":[190],"yields":[191],"more":[193],"efficient":[194],"Vina-FPGA2-Enhanced.":[197],"Finally,":[198],"experiments":[199],"show":[200],"that":[201],"Vina-FPGA2-Enhanced":[202],"achieves":[203,225],"average":[205],"12.6\u00d7":[206],"performance":[207],"improvement":[208,218],"over":[209,219],"central":[211],"processing":[212],"unit":[213],"(CPU)":[214],"3.3\u00d7":[217],"Compared":[221],"Vina-GPU,":[223],"Vina-FPGA2":[224],"7.2\u00d7":[227],"enhancement":[228],"energy":[230],"efficiency.":[231]},"counts_by_year":[],"updated_date":"2026-07-23T08:03:31.855105","created_date":"2025-12-03T00:00:00"}
