{"id":"https://openalex.org/W4414150262","doi":"https://doi.org/10.1631/fitee.2400677","title":"Algorithm and evaluation of generating pseudo-datasets for integrated circuit power analysis","display_name":"Algorithm and evaluation of generating pseudo-datasets for integrated circuit power analysis","publication_year":2025,"publication_date":"2025-09-01","ids":{"openalex":"https://openalex.org/W4414150262","doi":"https://doi.org/10.1631/fitee.2400677"},"language":"en","primary_location":{"id":"doi:10.1631/fitee.2400677","is_oa":false,"landing_page_url":"https://doi.org/10.1631/fitee.2400677","pdf_url":null,"source":{"id":"https://openalex.org/S4210189857","display_name":"Frontiers of Information Technology & Electronic Engineering","issn_l":"2095-9184","issn":["2095-9184","2095-9230"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Frontiers of Information Technology &amp; Electronic Engineering","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5104250319","display_name":"Zejia Lyu","orcid":"https://orcid.org/0009-0009-1019-5124"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zejia Lyu","raw_affiliation_strings":["College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, 310027, China"],"raw_orcid":"https://orcid.org/0009-0009-1019-5124","affiliations":[{"raw_affiliation_string":"College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, 310027, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043025337","display_name":"Jizhong Shen","orcid":"https://orcid.org/0000-0002-9031-2379"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jizhong Shen","raw_affiliation_strings":["College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, 310027, China"],"raw_orcid":"https://orcid.org/0000-0002-9031-2379","affiliations":[{"raw_affiliation_string":"College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, 310027, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006317498","display_name":"Xi Chen","orcid":"https://orcid.org/0000-0002-3057-0309"},"institutions":[{"id":"https://openalex.org/I4210146919","display_name":"Shanghai Industrial Technology Institute","ror":"https://ror.org/03j1pdd39","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210146919"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xi Chen","raw_affiliation_strings":["Shanghai Hexin Industrial Software Co., Ltd., Shanghai, 201210, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Shanghai Hexin Industrial Software Co., Ltd., Shanghai, 201210, China","institution_ids":["https://openalex.org/I4210146919"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5043025337"],"corresponding_institution_ids":["https://openalex.org/I76130692"],"apc_list":{"value":2990,"currency":"USD","value_usd":2990},"apc_paid":null,"fwci":1.0631,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.7908265,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"26","issue":"9","first_page":"1596","last_page":"1608"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-analysis","display_name":"Power analysis","score":0.7027999758720398},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5249999761581421},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.520799994468689},{"id":"https://openalex.org/keywords/network-analysis","display_name":"Network analysis","score":0.4957999885082245},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.49219998717308044},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.4771000146865845},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.46959999203681946},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4535999894142151},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4512999951839447},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.44690001010894775},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4120999872684479}],"concepts":[{"id":"https://openalex.org/C71743495","wikidata":"https://www.wikidata.org/wiki/Q2845210","display_name":"Power analysis","level":3,"score":0.7027999758720398},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6462000012397766},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5357999801635742},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5249999761581421},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.520799994468689},{"id":"https://openalex.org/C32946077","wikidata":"https://www.wikidata.org/wiki/Q618079","display_name":"Network analysis","level":2,"score":0.4957999885082245},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.49219998717308044},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.4771000146865845},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.46959999203681946},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4535999894142151},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4512999951839447},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.44690001010894775},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4120999872684479},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4106999933719635},{"id":"https://openalex.org/C106937863","wikidata":"https://www.wikidata.org/wiki/Q7236518","display_name":"Power graph analysis","level":3,"score":0.4092000126838684},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.40400001406669617},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.38519999384880066},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.38359999656677246},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.37299999594688416},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.37130001187324524},{"id":"https://openalex.org/C99149447","wikidata":"https://www.wikidata.org/wiki/Q5358339","display_name":"Electronic circuit design","level":3,"score":0.36070001125335693},{"id":"https://openalex.org/C168292644","wikidata":"https://www.wikidata.org/wiki/Q10860336","display_name":"Power optimization","level":4,"score":0.3573000133037567},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.349700003862381},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.3424000144004822},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.33629998564720154},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.329800009727478},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.32760000228881836},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.322299987077713},{"id":"https://openalex.org/C188058453","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Discrete circuit","level":4,"score":0.32010000944137573},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.3089999854564667},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.3043000102043152},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.28439998626708984},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.28349998593330383},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.28189998865127563},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.2775999903678894},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.2727000117301941},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.26269999146461487},{"id":"https://openalex.org/C159254197","wikidata":"https://www.wikidata.org/wiki/Q1144915","display_name":"Lexicographical order","level":2,"score":0.2614000141620636},{"id":"https://openalex.org/C51297928","wikidata":"https://www.wikidata.org/wiki/Q7001207","display_name":"Network synthesis filters","level":2,"score":0.2583000063896179},{"id":"https://openalex.org/C88230418","wikidata":"https://www.wikidata.org/wiki/Q131476","display_name":"Graph theory","level":2,"score":0.25679999589920044}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1631/fitee.2400677","is_oa":false,"landing_page_url":"https://doi.org/10.1631/fitee.2400677","pdf_url":null,"source":{"id":"https://openalex.org/S4210189857","display_name":"Frontiers of Information Technology & Electronic Engineering","issn_l":"2095-9184","issn":["2095-9184","2095-9230"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Frontiers of Information Technology &amp; Electronic Engineering","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W2112173236","https://openalex.org/W2124618076","https://openalex.org/W2137917061","https://openalex.org/W2152406824","https://openalex.org/W2615755298","https://openalex.org/W2936278485","https://openalex.org/W2945802982","https://openalex.org/W3027968530","https://openalex.org/W3036681545","https://openalex.org/W3042760681","https://openalex.org/W3092027164","https://openalex.org/W3146790333","https://openalex.org/W4205104605","https://openalex.org/W4286898282","https://openalex.org/W4291653274","https://openalex.org/W4293143707","https://openalex.org/W4293261952","https://openalex.org/W4296397626","https://openalex.org/W4353031973","https://openalex.org/W4364303268","https://openalex.org/W4377969843","https://openalex.org/W4384916994","https://openalex.org/W4387250981","https://openalex.org/W4389166667","https://openalex.org/W4389166679","https://openalex.org/W4401568756"],"related_works":["https://openalex.org/W2615598724","https://openalex.org/W2358304601","https://openalex.org/W154749848","https://openalex.org/W2365182058","https://openalex.org/W1739870862","https://openalex.org/W2099004443","https://openalex.org/W2461425825","https://openalex.org/W2148684293","https://openalex.org/W2079595599","https://openalex.org/W2327603067"],"abstract_inverted_index":{"Average":[0],"power":[1,60,117,123],"analysis":[2,61,118,143,147],"plays":[3],"a":[4,44,57,107],"crucial":[5],"role":[6],"in":[7,50],"the":[8,25,33,92,115,126,137,152,155,159,165],"design":[9,27],"of":[10,18,59,80,94,154,164],"large-scale":[11],"digital":[12],"integrated":[13],"circuits":[14],"(ICs).":[15],"The":[16,77,149],"integration":[17],"data-driven":[19],"machine":[20],"learning":[21],"(ML)":[22],"methods":[23],"into":[24,71,86],"electronic":[26],"automation":[28],"(EDA)":[29],"fields":[30],"has":[31],"increased":[32],"demand":[34],"for":[35],"extensive":[36],"datasets.":[37],"To":[38],"address":[39],"this":[40],"need,":[41],"we":[42],"propose":[43],"novel":[45],"pseudo-circuit":[46,108],"generation":[47],"algorithm":[48,54],"rooted":[49],"graph":[51],"topology.":[52],"This":[53],"efficiently":[55],"produces":[56],"multitude":[58],"examples":[62],"by":[63],"converting":[64],"randomly":[65],"generated":[66,127],"directed":[67],"acyclic":[68],"graphs":[69],"(DAGs)":[70],"gate-level":[72],"Verilog":[73],"pseudo-combinational":[74,84],"circuit":[75,88,95,140],"netlists.":[76,89],"subsequent":[78],"introduction":[79],"register":[81],"units":[82],"transforms":[83],"netlists":[85],"pseudo-sequential":[87],"Hyperparameters":[90],"facilitate":[91],"control":[93],"topology,":[96],"while":[97],"appropriate":[98],"sequential":[99],"constraints":[100],"are":[101],"applied":[102],"during":[103],"synthesis":[104],"to":[105],"yield":[106],"dataset.":[109],"We":[110],"evaluate":[111],"our":[112],"approach":[113],"using":[114],"mainstream":[116],"software,":[119],"conducting":[120],"pre-layout":[121],"average":[122],"tests":[124],"on":[125],"circuits,":[128],"comparing":[129],"their":[130],"performance":[131],"against":[132],"benchmark":[133],"datasets,":[134],"and":[135,144,157,162],"verifying":[136],"results":[138,150],"through":[139],"topology":[141],"complexity":[142],"static":[145],"timing":[146],"(STA).":[148],"confirm":[151],"effectiveness":[153],"dataset,":[156],"demonstrate":[158],"operational":[160],"efficiency":[161],"robustness":[163],"algorithm,":[166],"underscoring":[167],"its":[168],"research":[169],"value.":[170]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-23T08:03:31.855105","created_date":"2025-10-10T00:00:00"}
