{"id":"https://openalex.org/W3004552212","doi":"https://doi.org/10.1587/transinf.2020pap0015","title":"RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining","display_name":"RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining","publication_year":2020,"publication_date":"2020-11-30","ids":{"openalex":"https://openalex.org/W3004552212","doi":"https://doi.org/10.1587/transinf.2020pap0015","mag":"3004552212"},"language":"en","primary_location":{"id":"doi:10.1587/transinf.2020pap0015","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2020pap0015","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E103.D/12/E103.D_2020PAP0015/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["arxiv","crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://www.jstage.jst.go.jp/article/transinf/E103.D/12/E103.D_2020PAP0015/_pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103940031","display_name":"Hiromu Miyazaki","orcid":null},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Hiromu MIYAZAKI","raw_affiliation_strings":["School of Computing, Tokyo Institute of Technology"],"affiliations":[{"raw_affiliation_string":"School of Computing, Tokyo Institute of Technology","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083905038","display_name":"Takuto Kanamori","orcid":null},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takuto KANAMORI","raw_affiliation_strings":["School of Computing, Tokyo Institute of Technology"],"affiliations":[{"raw_affiliation_string":"School of Computing, Tokyo Institute of Technology","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100658058","display_name":"Md. Ashraful Islam","orcid":"https://orcid.org/0000-0001-9412-9478"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Md Ashraful ISLAM","raw_affiliation_strings":["School of Computing, Tokyo Institute of Technology"],"affiliations":[{"raw_affiliation_string":"School of Computing, Tokyo Institute of Technology","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010523030","display_name":"Kenji Kise","orcid":"https://orcid.org/0000-0002-3003-4872"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenji KISE","raw_affiliation_strings":["School of Computing, Tokyo Institute of Technology"],"affiliations":[{"raw_affiliation_string":"School of Computing, Tokyo Institute of Technology","institution_ids":["https://openalex.org/I114531698"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5103940031"],"corresponding_institution_ids":["https://openalex.org/I114531698"],"apc_list":null,"apc_paid":null,"fwci":1.2481,"has_fulltext":true,"cited_by_count":21,"citation_normalized_percentile":{"value":0.79010768,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"E103.D","issue":"12","first_page":"2494","last_page":"2503"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8635682463645935},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7425448298454285},{"id":"https://openalex.org/keywords/software-pipelining","display_name":"Software pipelining","score":0.7061916589736938},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.6560240983963013},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.2867870330810547},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23078447580337524},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.0659211277961731}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8635682463645935},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7425448298454285},{"id":"https://openalex.org/C188854837","wikidata":"https://www.wikidata.org/wiki/Q268469","display_name":"Software pipelining","level":3,"score":0.7061916589736938},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.6560240983963013},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.2867870330810547},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23078447580337524},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.0659211277961731}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1587/transinf.2020pap0015","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2020pap0015","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E103.D/12/E103.D_2020PAP0015/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"},{"id":"pmh:oai:arXiv.org:2002.03568","is_oa":true,"landing_page_url":"http://arxiv.org/abs/2002.03568","pdf_url":"https://arxiv.org/pdf/2002.03568","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"}],"best_oa_location":{"id":"doi:10.1587/transinf.2020pap0015","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2020pap0015","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E103.D/12/E103.D_2020PAP0015/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G5786340949","display_name":null,"funder_award_id":"KAKENHI Grant Number","funder_id":"https://openalex.org/F4320334764","funder_display_name":"Japan Society for the Promotion of Science"},{"id":"https://openalex.org/G7525915324","display_name":"Research on High-speed Emulation of Large Scale Many-core Processors","funder_award_id":"16H02794","funder_id":"https://openalex.org/F4320334764","funder_display_name":"Japan Society for the Promotion of Science"}],"funders":[{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3004552212.pdf","grobid_xml":"https://content.openalex.org/works/W3004552212.grobid-xml"},"referenced_works_count":14,"referenced_works":["https://openalex.org/W220440441","https://openalex.org/W1567646530","https://openalex.org/W1983394510","https://openalex.org/W2002752493","https://openalex.org/W2004340162","https://openalex.org/W2013129990","https://openalex.org/W2158441333","https://openalex.org/W2892310816","https://openalex.org/W2956501515","https://openalex.org/W2991607219","https://openalex.org/W3003778129","https://openalex.org/W3147312088","https://openalex.org/W3152709722","https://openalex.org/W4245804582"],"related_works":["https://openalex.org/W2389666628","https://openalex.org/W1603958403","https://openalex.org/W1976397984","https://openalex.org/W4232563190","https://openalex.org/W2034393996","https://openalex.org/W1816081266","https://openalex.org/W1567574506","https://openalex.org/W4313417926","https://openalex.org/W2571417379","https://openalex.org/W2117559535"],"abstract_inverted_index":{"RISC-V":[0,35],"is":[1,36,41,145],"a":[2,146],"RISC":[3],"based":[4],"open":[5,149],"and":[6,18,49,91,101,108,126,148],"loyalty":[7],"free":[8],"instruction":[9,32,85],"set":[10,33],"architecture":[11],"which":[12,40,144],"has":[13],"been":[14],"developed":[15],"since":[16],"2010,":[17],"can":[19],"be":[20],"used":[21],"for":[22,51],"cost-effective":[23],"soft":[24,62],"processors":[25],"on":[26],"FPGAs.":[27],"The":[28],"basic":[29],"32-bit":[30],"integer":[31],"in":[34,98],"defined":[37],"as":[38],"RV32I,":[39],"sufficient":[42],"to":[43,74,77],"support":[44],"the":[45,75,79,103,130],"operating":[46,80,121],"system":[47],"environment":[48],"suits":[50],"embedded":[52],"systems.":[53],"In":[54],"this":[55],"paper,":[56],"we":[57,133],"propose":[58],"an":[59,109],"optimized":[60],"RV32I":[61,151],"processor":[63,76,127,152],"named":[64],"RVCoreP":[65,97,136],"adopting":[66],"five-stage":[67],"pipelining.":[68],"Three":[69],"effective":[70],"methods":[71,83],"are":[72,84],"applied":[73],"improve":[78],"frequency.":[81],"These":[82],"fetch":[86],"unit":[87],"optimization,":[88,90],"ALU":[89],"data":[92],"memory":[93],"optimization.":[94],"We":[95,115],"implement":[96],"Verilog":[99,106],"HDL":[100],"verify":[102],"behavior":[104],"using":[105],"simulation":[107],"actual":[110],"Xilinx":[111],"Atrix-7":[112],"FPGA":[113],"board.":[114],"evaluate":[116],"IPC":[117],"(instructions":[118],"per":[119],"cycle),":[120],"frequency,":[122],"hardware":[123],"resource":[124],"utilization,":[125],"performance.":[128],"From":[129],"evaluation":[131],"results,":[132],"show":[134],"that":[135],"achieves":[137],"30.0%":[138],"performance":[139],"improvement":[140],"compared":[141],"with":[142],"VexRiscv,":[143],"high-performance":[147],"source":[150],"selected":[153],"from":[154],"some":[155],"related":[156],"works.":[157]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":2}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}
