{"id":"https://openalex.org/W3007726992","doi":"https://doi.org/10.1587/transinf.2019edp7144","title":"Daisy-Chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth","display_name":"Daisy-Chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth","publication_year":2020,"publication_date":"2020-02-29","ids":{"openalex":"https://openalex.org/W3007726992","doi":"https://doi.org/10.1587/transinf.2019edp7144","mag":"3007726992"},"language":"en","primary_location":{"id":"doi:10.1587/transinf.2019edp7144","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2019edp7144","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E103.D/3/E103.D_2019EDP7144/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://www.jstage.jst.go.jp/article/transinf/E103.D/3/E103.D_2019EDP7144/_pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088555482","display_name":"Jun Iwamoto","orcid":null},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Jun IWAMOTO","raw_affiliation_strings":["Nara Institute of Science and Technology"],"affiliations":[{"raw_affiliation_string":"Nara Institute of Science and Technology","institution_ids":["https://openalex.org/I75917431"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034006728","display_name":"Yuma Kikutani","orcid":null},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yuma KIKUTANI","raw_affiliation_strings":["Nara Institute of Science and Technology"],"affiliations":[{"raw_affiliation_string":"Nara Institute of Science and Technology","institution_ids":["https://openalex.org/I75917431"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101464173","display_name":"Renyuan Zhang","orcid":"https://orcid.org/0000-0002-2635-2077"},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Renyuan ZHANG","raw_affiliation_strings":["Nara Institute of Science and Technology"],"affiliations":[{"raw_affiliation_string":"Nara Institute of Science and Technology","institution_ids":["https://openalex.org/I75917431"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074853381","display_name":"Yasuhiko Nakashima","orcid":"https://orcid.org/0000-0002-9457-5061"},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yasuhiko NAKASHIMA","raw_affiliation_strings":["Nara Institute of Science and Technology"],"affiliations":[{"raw_affiliation_string":"Nara Institute of Science and Technology","institution_ids":["https://openalex.org/I75917431"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5088555482"],"corresponding_institution_ids":["https://openalex.org/I75917431"],"apc_list":null,"apc_paid":null,"fwci":1.1552,"has_fulltext":true,"cited_by_count":7,"citation_normalized_percentile":{"value":0.75275842,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"E103.D","issue":"3","first_page":"578","last_page":"589"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8108691573143005},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6826828122138977},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.6061453819274902},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5285707116127014},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5129470229148865},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.48833271861076355},{"id":"https://openalex.org/keywords/precomputation","display_name":"Precomputation","score":0.4813854992389679},{"id":"https://openalex.org/keywords/memory-footprint","display_name":"Memory footprint","score":0.41945868730545044},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4149358868598938},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.41222789883613586},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3799367845058441},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.2530626654624939},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.21681365370750427}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8108691573143005},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6826828122138977},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.6061453819274902},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5285707116127014},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5129470229148865},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.48833271861076355},{"id":"https://openalex.org/C159379195","wikidata":"https://www.wikidata.org/wiki/Q7239568","display_name":"Precomputation","level":3,"score":0.4813854992389679},{"id":"https://openalex.org/C74912251","wikidata":"https://www.wikidata.org/wiki/Q6815727","display_name":"Memory footprint","level":2,"score":0.41945868730545044},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4149358868598938},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.41222789883613586},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3799367845058441},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.2530626654624939},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.21681365370750427},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/transinf.2019edp7144","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2019edp7144","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E103.D/3/E103.D_2019EDP7144/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1587/transinf.2019edp7144","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2019edp7144","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E103.D/3/E103.D_2019EDP7144/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5600000023841858,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3007726992.pdf","grobid_xml":"https://content.openalex.org/works/W3007726992.grobid-xml"},"referenced_works_count":21,"referenced_works":["https://openalex.org/W105298322","https://openalex.org/W1575535798","https://openalex.org/W1686810756","https://openalex.org/W1841592590","https://openalex.org/W1980329590","https://openalex.org/W2036823494","https://openalex.org/W2044831861","https://openalex.org/W2097117768","https://openalex.org/W2100846455","https://openalex.org/W2194775991","https://openalex.org/W2571825367","https://openalex.org/W2606722458","https://openalex.org/W2612076670","https://openalex.org/W2618530766","https://openalex.org/W2624998622","https://openalex.org/W2805426800","https://openalex.org/W2950656546","https://openalex.org/W3024621361","https://openalex.org/W3152199537","https://openalex.org/W4251954698","https://openalex.org/W4253108260"],"related_works":["https://openalex.org/W126258643","https://openalex.org/W2157769033","https://openalex.org/W2096978683","https://openalex.org/W414359703","https://openalex.org/W2687399516","https://openalex.org/W2543067032","https://openalex.org/W2170398238","https://openalex.org/W3029113864","https://openalex.org/W2020308516","https://openalex.org/W1536156622"],"abstract_inverted_index":{"A":[0],"paradigm":[1],"shift":[2],"toward":[3],"edge":[4],"computing":[5],"infrastructures":[6],"that":[7],"prioritize":[8],"small":[9],"footprint":[10,26],"and":[11,27,43,63,85,114,130,139,142,208],"scalable/easy-to-estimate":[12],"performance":[13,46,116,211],"is":[14,169,190,202,214],"increasing.":[15],"In":[16],"this":[17],"paper,":[18],"we":[19],"propose":[20],"the":[21,25,28,38,45,82,112,115,132,144,147,163,166,183,197,209],"following":[22],"to":[23,121],"improve":[24],"scalability":[29],"of":[30,40,92,150,165,199,206],"systolic":[31,98,179],"arrays:":[32],"(1)":[33,146],"column":[34,103],"multithreading":[35],"for":[36,48,58,70,80,89],"reducing":[37,81],"number":[39],"physical":[41],"units":[42],"maintaining":[44],"even":[47],"back-to-back":[49],"floating-point":[50],"accumulations;":[51],"(2)":[52,182],"a":[53,59,97,101,122,135,151,177,187,200],"cascaded":[54],"peer-to-peer":[55],"AXI":[56,127],"bus":[57,69],"scalable":[60],"multichip":[61],"structure":[62],"an":[64,118,126],"intra-chip":[65],"parallel":[66],"local":[67,93,167],"memory":[68,140],"low":[71],"latency;":[72],"(3)":[73,196],"multilevel":[74],"loop":[75],"control":[76],"in":[77],"any":[78],"unit":[79],"startup":[83],"overhead":[84],"adaptive":[86],"operation":[87],"shifting":[88],"efficient":[90],"reuse":[91],"memories.":[94],"We":[95],"designed":[96],"array":[99,180],"with":[100,108,134,176,186],"single":[102],"\u00d7":[104],"64":[105],"row":[106],"configuration":[107,189],"Verilog":[109],"HDL,":[110],"evaluated":[111,131],"frequency":[113],"on":[117],"FPGA":[119],"attached":[120],"ZYNQ":[123],"system":[124],"as":[125],"slave":[128],"device,":[129],"area":[133,213],"TSMC":[136],"28nm":[137],"library":[138],"generator":[141],"identified":[143],"following:":[145],"execution":[148],"speed":[149,185],"matrix":[152],"multiplication/a":[153],"convolution":[154],"operation/a":[155],"light-field":[156],"depth":[157],"extraction,":[158],"whose":[159],"size":[160,198],"larger":[161],"than":[162],"capacity":[164],"memory,":[168],"6.3\u00d7":[170],"/":[171,173,192,194],"9.2\u00d7":[172],"6.6\u00d7":[174],"compared":[175],"similar":[178],"(EMAX);":[181],"estimated":[184],"4-chip":[188],"19.6\u00d7":[191],"16.0\u00d7":[193],"8.5\u00d7;":[195],"single-chip":[201],"8.4":[203],"mm2":[204],"(0.31\u00d7":[205],"EMAX)":[207],"basic":[210],"per":[212],"2.4\u00d7.":[215]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}