{"id":"https://openalex.org/W2786628740","doi":"https://doi.org/10.1587/transinf.2017rcp0008","title":"Three Dimensional FPGA Architecture with Fewer TSVs","display_name":"Three Dimensional FPGA Architecture with Fewer TSVs","publication_year":2018,"publication_date":"2018-01-01","ids":{"openalex":"https://openalex.org/W2786628740","doi":"https://doi.org/10.1587/transinf.2017rcp0008","mag":"2786628740"},"language":"en","primary_location":{"id":"doi:10.1587/transinf.2017rcp0008","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2017rcp0008","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E101.D/2/E101.D_2017RCP0008/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://www.jstage.jst.go.jp/article/transinf/E101.D/2/E101.D_2017RCP0008/_pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012465812","display_name":"Motoki Amagasaki","orcid":"https://orcid.org/0000-0002-5196-9765"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Motoki AMAGASAKI","raw_affiliation_strings":["Faculty of Advanced Science and Technology, Kumamoto University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Advanced Science and Technology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034152964","display_name":"Ikebe Masato","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masato IKEBE","raw_affiliation_strings":["Faculty of Advanced Science and Technology, Kumamoto University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Advanced Science and Technology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051831948","display_name":"Qian Zhao","orcid":"https://orcid.org/0000-0003-0032-1974"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Qian ZHAO","raw_affiliation_strings":["Faculty of Advanced Science and Technology, Kumamoto University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Advanced Science and Technology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059705629","display_name":"Masahiro Iida","orcid":"https://orcid.org/0000-0002-9654-2319"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro IIDA","raw_affiliation_strings":["Faculty of Advanced Science and Technology, Kumamoto University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Advanced Science and Technology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031401749","display_name":"Toshinori Sueyoshi","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toshinori SUEYOSHI","raw_affiliation_strings":["Faculty of Advanced Science and Technology, Kumamoto University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Advanced Science and Technology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3928,"has_fulltext":true,"cited_by_count":4,"citation_normalized_percentile":{"value":0.61645005,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"E101.D","issue":"2","first_page":"278","last_page":"287"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9419384002685547},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7598096132278442},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.7193892002105713},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.584071934223175},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5331100225448608},{"id":"https://openalex.org/keywords/stacking","display_name":"Stacking","score":0.4846830666065216},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.4610857367515564},{"id":"https://openalex.org/keywords/face","display_name":"Face (sociological concept)","score":0.4308600127696991},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.41262075304985046},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40924501419067383},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3683571219444275},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.28773772716522217},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.10789409279823303}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9419384002685547},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7598096132278442},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.7193892002105713},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.584071934223175},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5331100225448608},{"id":"https://openalex.org/C33347731","wikidata":"https://www.wikidata.org/wiki/Q285210","display_name":"Stacking","level":2,"score":0.4846830666065216},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.4610857367515564},{"id":"https://openalex.org/C2779304628","wikidata":"https://www.wikidata.org/wiki/Q3503480","display_name":"Face (sociological concept)","level":2,"score":0.4308600127696991},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.41262075304985046},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40924501419067383},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3683571219444275},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.28773772716522217},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.10789409279823303},{"id":"https://openalex.org/C144024400","wikidata":"https://www.wikidata.org/wiki/Q21201","display_name":"Sociology","level":0,"score":0.0},{"id":"https://openalex.org/C36289849","wikidata":"https://www.wikidata.org/wiki/Q34749","display_name":"Social science","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C46141821","wikidata":"https://www.wikidata.org/wiki/Q209402","display_name":"Nuclear magnetic resonance","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/transinf.2017rcp0008","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2017rcp0008","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E101.D/2/E101.D_2017RCP0008/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1587/transinf.2017rcp0008","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2017rcp0008","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E101.D/2/E101.D_2017RCP0008/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.5400000214576721,"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2786628740.pdf","grobid_xml":"https://content.openalex.org/works/W2786628740.grobid-xml"},"referenced_works_count":15,"referenced_works":["https://openalex.org/W1473376696","https://openalex.org/W1977850862","https://openalex.org/W2059612698","https://openalex.org/W2070232376","https://openalex.org/W2093426958","https://openalex.org/W2095841863","https://openalex.org/W2103755335","https://openalex.org/W2128473621","https://openalex.org/W2139243942","https://openalex.org/W2145036220","https://openalex.org/W2168493238","https://openalex.org/W2170034300","https://openalex.org/W3140592728","https://openalex.org/W3143097289","https://openalex.org/W4248651289"],"related_works":["https://openalex.org/W2998132311","https://openalex.org/W2164041287","https://openalex.org/W2207067480","https://openalex.org/W4383823603","https://openalex.org/W2406926880","https://openalex.org/W2332075903","https://openalex.org/W1579891439","https://openalex.org/W2291257309","https://openalex.org/W272033699","https://openalex.org/W1692883217"],"abstract_inverted_index":{"Three-dimensional":[0],"(3D)":[1],"field-programmable":[2],"gate":[3],"arrays":[4],"(FPGAs)":[5],"are":[6],"expected":[7],"to":[8,61,103,129,138,152],"offer":[9],"higher":[10],"logic":[11],"density":[12],"as":[13,15],"well":[14],"improved":[16],"delay":[17],"and":[18,49,58,60,77],"power":[19],"performance":[20,147],"by":[21],"utilizing":[22],"3D":[23,33,63,67,75,92,143,158],"integrated":[24],"circuit":[25],"technology.":[26],"However,":[27],"because":[28],"through-silicon-vias":[29],"(TSVs)":[30],"for":[31,82,132],"conventional":[32],"FPGA":[34,76,93,144,159],"interlayer":[35],"connections":[36],"have":[37],"a":[38,54,90,95,141,156,161],"large":[39],"area":[40,165],"overhead,":[41],"there":[42],"is":[43,160,166],"an":[44],"inherent":[45],"tradeoff":[46],"between":[47,56],"connectivity":[48],"small":[50],"size.":[51],"To":[52,119],"find":[53],"balance":[55],"cost":[57],"performance,":[59],"explore":[62],"FPGAs":[64,131],"with":[65,94,134],"realistic":[66],"integration":[68,97],"processes,":[69],"we":[70,88,109,125],"propose":[71],"two":[72,104,153],"types":[73],"of":[74,114,123],"construct":[78],"design":[79,151],"tool":[80],"sets":[81],"architecture":[83],"exploration.":[84],"In":[85,106],"previous":[86],"research,":[87],"created":[89],"TSV-free":[91],"face-down":[96,116],"method;":[98],"however,":[99],"this":[100,107],"was":[101],"limited":[102],"layers.":[105,136],"paper,":[108],"discuss":[110],"the":[111,121,130,150],"face-up":[112],"stacking":[113],"several":[115],"stacked":[117],"FPGAs.":[118],"minimize":[120],"number":[122],"TSVs,":[124],"placed":[126],"TSVs":[127],"peripheral":[128],"3D-FPGA":[133],"4":[135],"According":[137],"our":[139],"results,":[140],"2-layer":[142],"has":[145],"reasonable":[146],"when":[148,164],"limiting":[149],"layers,":[154],"but":[155],"4-layer":[157],"better":[162],"choice":[163],"emphasized.":[167]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
